parameters.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	parameters
// Design: 	CAM_Top 
// Verilog code:	Defines Parameters for CAM design
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 - Option = Preserve Hierarchy
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: This file defines the Data path and Address widths
// 	        of the CAM design as well as some synthesis and
//              simulation options
//
// Device: 	VIRTEX Families
//
// Created by: Brian Philofsky / XILINX Design Center
// Modified by: Maria George   / XILINX APPLICATIONS ENGR
// Date: September 8, 1999
// Version: 1.1
//
// History: 
//     1.  09/08/99 BP:  Created File
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-



/////////////////////////////////////////////////////
// Un-comment any group of two define statements //
//         below signifying CAM size               //
/////////////////////////////////////////////////////

`define nb_cam16x8s 2
`define addr_width 5

// `define nb_cam16x8s 4
// `define addr_width 6

// `define nb_cam16x8s 8
// `define addr_width 7

// `define nb_cam16x8s 16
// `define addr_width 8


///////////////////////////////////////////////////////////////////
// Comment or uncomment the following define statement to choose //
//  to construct large multiplexors out of T-BUFs or use gates   //
///////////////////////////////////////////////////////////////////

// `define use_gates_for_large_muxes


/////////////////////////////////////////////////////////////
// Specify the clock period for the simulation test bench //
// Note: This will not be passed as a timing constraint   //
////////////////////////////////////////////////////////////

`define clock_period 10


/////////////////////////////////////
// Use ADDR_VALID (Larger circuit) //
/////////////////// /////////////////

//`define use_addr_valid