inport.v

DE1-FPGA-Board

//
// FPGA PACMAN I/O interface
//
// Version : beta1
//
// Copyright(c) 2002 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use. 
// An author does no guarantee about this program.
// You can use this under your own risk. 
//
//

module inport(
// inputs
	LEFT1,
	RIGHT1,
	UP1,
	DOWN1,
	LEFT2,
	RIGHT2,
	UP2,
	DOWN2,
	START1,
	START2,
	COIN1,
	COIN2,
	CREDIT,
	TEST,
	TABLE,
//enables
	IN0,
	IN1,
	DSW1,
	DSW2,
// output
	DO);

input IN0;
input IN1;
input DSW1;
input DSW2;
input LEFT1,RIGHT1,UP1,DOWN1;
input LEFT2,RIGHT2,UP2,DOWN2;
input START1,START2,COIN1,COIN2;
input CREDIT,TEST,TABLE;
output [7:0] DO;

wire [7:0] in0do,in1do,ds1do,ds2do;

//IN0
wire DSW16 = 1'b1;

//coinage : FREE , 1C/1C , 1C/2C , 2C/1C
wire [1:0] COINAGE = 2'b01;
//lives : 1 , 2 , 3 , 5
wire [1:0] LIVES  = 2'b10;
//bonus : 10000 , 15000 , 20000 , NONE
wire [1:0] BONUS  = 2'b00;
//diffic : hard , normal
wire DIFFI  = 1'b1;
//GNAME  : 
wire GNAME = 1'b1;

assign in0do = IN0 ? { CREDIT,COIN2,COIN1,DSW16,DOWN1,RIGHT1,LEFT1,UP1 } : 8'h00;
assign in1do = IN1 ? { TABLE ,START2,START1,TEST,DOWN2,RIGHT2,LEFT2,UP2 } : 8'h00;
assign ds1do = DSW1 ? { GNAME,DIFFI,BONUS,LIVES,COINAGE } : 8'h00;
assign ds2do = DSW2 ? 8'b11111111 : 8'h00;

assign DO = in0do | in1do | ds1do | ds2do;

endmodule