z80ip_t.v

来自「DE1-FPGA-Board」· Verilog 代码 · 共 65 行

//
// FPGA PACMAN Z80 interface for Daniel Wallner's T80
//
// Version : beta2
//
// Copyright(c) 2002,2003 Tatsuyuki Satoh , All rights reserved
//
// Important !
//
// This program is freeware for non-commercial use. 
// An author does no guarantee about this program.
// You can use this under your own risk. 
//

//
// necessary lisence:
//
// see T80_cpu information in OPENCORES.ORG.
// <http://www.opencores.org/projects/t80/>
//

// necessary files:
//
// 1.T80S.NGC(Write protected) : synthesized T80S netlist ver.0240 or later
// 2.T80S.jhd(Write protected) : T80S tree file
// 2.T80S.V                    : T80S Verilog I/F file
//

module Z80IP(
	A,	DIN,	DOUT,	BUSWO,
	RESET_N,	INT_N,	NMI_N, WAIT_N,
	M1_N,	MREQ_N,	IORQ_N,	RD_N,	WR_N,
	RFSH_N,	HALT_N,	CLK2X,CLK);

// I/O assign
output [15:0] A;
input  [7:0] DIN;
output [7:0] DOUT;
input  RESET_N,INT_N,NMI_N,WAIT_N,CLK2X,CLK;
output M1_N,MREQ_N,IORQ_N,RD_N,WR_N,RFSH_N,HALT_N,BUSWO;

// Z80IP interface
T80as z80core (
	.RESET_n(RESET_N),
	.CLK_n(CLK),
	.WAIT_n(WAIT_N),
	.INT_n(INT_N),
	.NMI_n(NMI_N),
	.BUSRQ_n(1'b1),
	.M1_n(M1_N),
	.MREQ_n(MREQ_N),
	.IORQ_n(IORQ_N),
	.RD_n(RD_N),
	.WR_n(WR_N),
	.RFSH_n(RFSH_N),
	.HALT_n(HALT_N),
	.BUSAK_n(),
	.A(A),
	.DI(DIN),
	.DO(DOUT),
	.DOE(BUSWO)
);

endmodule