代码搜索结果

C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/vhdl/lab2/kcuart_rx.vhd C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/vhdl/lab2/uart_rx.vhd C:/X

C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/vhdl/lab3/time_const/kcuart_rx.vhd C:/XUP/Markets/PLDs/Workshops/courses/v81_fpga_flow/xupv2pro/labsolutions/vhdl/lab3/time_c

V3 5 FL G:/fpga/20Example/Music_HLD3/lkmusic/top.vhd 2008/06/05.18:05:38 I.24 EN work/musicdec 1212660342 FL G:/fpga/20Example/Music_HLD3/lkmusic/top.vhd \ PB ieee/std_logic_1164 11311

m255 13 cModel Technology dE:\FPGA\xinkaifabanshiyan\zijizuode\UART\simulation\modelsim\receiver vuart I?5VUZVS22^Q4nC2Ygfn9z2 VAL6N^fD0gW8?XcVf`QkZQ2 dE:\FPGA\xinkaifabanshiyan\zijizuode\S7_UART\phys

E:/FPGA/xinkaifabanshiyan/EP2C35/S7_UART/Src/uart.v {1 {vlog -work work -novopt E:/FPGA/xinkaifabanshiyan/EP2C35/S7_UART/Src/uart.v Model Technology ModelSim SE vlog 6.1f Compiler 2006.05 May 12 2006

/README/1.1.1.1/Sun Mar 13 21:26:12 2005//Tbranch_R06R2 /fpga.c/1.1.1.1/Sun Mar 13 21:26:12 2005//Tbranch_R06R2 /fpga.h/1.1.1.1/Sun Mar 13 21:26:12 2005//Tbranch_R06R2 D

#---------------------------------------------------------- # Synopsys FPGA Compiler II simulation script verilog.fc2 # for the book: Digital Signal Processing with FPGAs # Author-EMAIL: Uwe.Meyer

#---------------------------------------------------------- # Synopsys FPGA Compiler II simulation script verilog.fc2 # for the book: Digital Signal Processing with FPGAs # Author-EMAIL: Uwe.Meyer

//////////////////////////////////////////////////// // // High Speed tap8 DDS for altera fpga // Using for connecting Ghz DA to synthesis wave // // Coder: Yang Guojiang // Copyright Jan 2009 Ya

# *** UCF for DDR2_DIMM5 interface on FPGA2 device *** # ################################################################################### # *** UCF generated by a script from ML561 Board Layout Net