mem_tb_top.ucf

xilinx公司的ＤＤＲ实现源码

# *** UCF for DDR2_DIMM5 interface on FPGA2 device ***
# ###################################################################################
# *** UCF generated by a script from ML561 Board Layout Netlist file ***
#
#NET  <Memory Controller Signal>     LOC =   <Pin> ;   # <Board Signal name> 
# -----------------------------------------------------------------------------------
#NET "mem_clk_rst/sys_rst*" TIG;
#NET "mem_clk_rst/sys_rst_*" TIG;
NET 	 "cntrl0_DDR2_A[0]" 	 LOC = 	 "AG30" ; 	 # DDR2_DIMM_A0
NET 	 "cntrl0_DDR2_A[1]" 	 LOC = 	 "AH29" ; 	 # DDR2_DIMM_A1
NET 	 "cntrl0_DDR2_A[2]" 	 LOC = 	 "AH30" ; 	 # DDR2_DIMM_A2
NET 	 "cntrl0_DDR2_A[3]" 	 LOC = 	 "AJ30" ; 	 # DDR2_DIMM_A3
NET 	 "cntrl0_DDR2_A[4]" 	 LOC = 	 "AF30" ; 	 # DDR2_DIMM_A4
NET 	 "cntrl0_DDR2_A[5]" 	 LOC = 	 "AF29" ; 	 # DDR2_DIMM_A5
NET 	 "cntrl0_DDR2_A[6]" 	 LOC = 	 "AK31" ; 	 # DDR2_DIMM_A6
NET 	 "cntrl0_DDR2_A[7]" 	 LOC = 	 "AJ31" ; 	 # DDR2_DIMM_A7
NET 	 "cntrl0_DDR2_A[8]" 	 LOC = 	 "AD29" ; 	 # DDR2_DIMM_A8
NET 	 "cntrl0_DDR2_A[9]" 	 LOC = 	 "AE29" ; 	 # DDR2_DIMM_A9
NET 	 "cntrl0_DDR2_A[10]" 	 LOC = 	 "AF31" ; 	 # DDR2_DIMM_A10
NET 	 "cntrl0_DDR2_A[11]" 	 LOC = 	 "AC29" ; 	 # DDR2_DIMM_A11
NET 	 "cntrl0_DDR2_A[12]" 	 LOC = 	 "AD30" ; 	 # DDR2_DIMM_A12
NET 	 "cntrl0_DDR2_A[13]" 	 LOC = 	 "AA30" ; 	 # DDR2_DIMM_A13
#NET 	 "cntrl0_DDR2_A[14]" 	 LOC = 	 "AA29" ; 	 # DDR2_DIMM_A14
#NET 	 "cntrl0_DDR2_A[15]" 	 LOC = 	 "AC30" ; 	 # DDR2_DIMM_A15
NET 	 "cntrl0_DDR2_BA[0]" 	 LOC = 	 "AB30" ; 	 # DDR2_DIMM_BA0
NET 	 "cntrl0_DDR2_BA[1]" 	 LOC = 	 "AA31" ; 	 # DDR2_DIMM_BA1
#NET 	 "cntrl0_DDR2_BA[2]" 	 LOC = 	 "AB31" ; 	 # DDR2_DIMM_BA2
NET 	 "cntrl0_DDR2_CAS_N" 	 LOC = 	 "V29" ; 	 # DDR2_DIMM_CAS_N
NET 	 "cntrl0_DDR2_RAS_N" 	 LOC = 	 "Y28" ; 	 # DDR2_DIMM_RAS_N
NET 	 "cntrl0_DDR2_RESET_N" 	 LOC = 	 "Y29" ; 	 # DDR2_DIMM_RESET_N
NET 	 "cntrl0_DDR2_WE_N" 	 LOC = 	 "W29" ; 	 # DDR2_DIMM_WE_N

NET 	 "cntrl0_DDR2_DM[0]" 	 LOC = 	 "U30" ; 	 # DDR2_DIMM_DM_DQS_BY8_H_P
NET 	 "cntrl0_DDR2_DM[1]" 	 LOC = 	 "R31" ; 	 # DDR2_DIMM_DM_DQS_BY9_H_P
NET 	 "cntrl0_DDR2_DM[2]" 	 LOC = 	 "T31" ; 	 # DDR2_DIMM_DM_DQS_BY10_H_P
NET 	 "cntrl0_DDR2_DM[3]" 	 LOC = 	 "L33" ; 	 # DDR2_DIMM_DM_DQS_BY11_H_P
NET 	 "cntrl0_DDR2_DM[4]" 	 LOC = 	 "AK34" ; 	 # DDR2_DIMM_DM_DQS_BY12_H_P
NET 	 "cntrl0_DDR2_DM[5]" 	 LOC = 	 "AG32" ; 	 # DDR2_DIMM_DM_DQS_BY13_H_P
NET 	 "cntrl0_DDR2_DM[6]" 	 LOC = 	 "P34" ; 	 # DDR2_DIMM_DM_DQS_BY14_H_P
NET 	 "cntrl0_DDR2_DM[7]" 	 LOC = 	 "AK33" ; 	 # DDR2_DIMM_DM_DQS_BY15_H_P


NET 	 "cntrl0_DDR2_DQS_N[0]"  LOC = 	 "N30" ; 	 # DDR2_DIMM_DQS_BY8_L_N
NET 	 "cntrl0_DDR2_DQS[0]" 	 LOC = 	 "M31" ; 	 # DDR2_DIMM_DQS_BY8_L_P
NET 	 "cntrl0_DDR2_DQS_N[1]"  LOC = 	 "P30" ; 	 # DDR2_DIMM_DQS_BY9_L_N
NET 	 "cntrl0_DDR2_DQS[1]" 	 LOC = 	 "P31" ; 	 # DDR2_DIMM_DQS_BY9_L_P
NET 	 "cntrl0_DDR2_DQS_N[2]"  LOC = 	 "L31" ; 	 # DDR2_DIMM_DQS_BY10_L_N
NET 	 "cntrl0_DDR2_DQS[2]" 	 LOC = 	 "K31" ; 	 # DDR2_DIMM_DQS_BY10_L_P
NET 	 "cntrl0_DDR2_DQS_N[3]"  LOC = 	 "J34" ; 	 # DDR2_DIMM_DQS_BY11_L_N
NET 	 "cntrl0_DDR2_DQS[3]" 	 LOC = 	 "H34" ; 	 # DDR2_DIMM_DQS_BY11_L_P
NET 	 "cntrl0_DDR2_DQS_N[4]"  LOC = 	 "AE34" ; 	 # DDR2_DIMM_DQS_BY12_L_N
NET 	 "cntrl0_DDR2_DQS[4]" 	 LOC = 	 "AF34" ; 	 # DDR2_DIMM_DQS_BY12_L_P
NET 	 "cntrl0_DDR2_DQS_N[5]"  LOC = 	 "AE32" ; 	 # DDR2_DIMM_DQS_BY13_L_N
NET 	 "cntrl0_DDR2_DQS[5]" 	 LOC = 	 "AD32" ; 	 # DDR2_DIMM_DQS_BY13_L_P
NET 	 "cntrl0_DDR2_DQS_N[6]"  LOC = 	 "K32" ; 	 # DDR2_DIMM_DQS_BY14_L_N
NET 	 "cntrl0_DDR2_DQS[6]" 	 LOC = 	 "K33" ; 	 # DDR2_DIMM_DQS_BY14_L_P
NET 	 "cntrl0_DDR2_DQS_N[7]"  LOC = 	 "AJ34" ; 	 # DDR2_DIMM_DQS_BY15_L_N
NET 	 "cntrl0_DDR2_DQS[7]" 	 LOC = 	 "AH34" ; 	 # DDR2_DIMM_DQS_BY15_L_P


NET 	 "cntrl0_DDR2_DQ[0]" 	 LOC = 	 "T25" ; 	 # DDR2_DIMM_DQ_BY0_B0
NET 	 "cntrl0_DDR2_DQ[1]" 	 LOC = 	 "U25" ; 	 # DDR2_DIMM_DQ_BY0_B1
NET 	 "cntrl0_DDR2_DQ[2]" 	 LOC = 	 "T26" ; 	 # DDR2_DIMM_DQ_BY0_B2
NET 	 "cntrl0_DDR2_DQ[3]" 	 LOC = 	 "U26" ; 	 # DDR2_DIMM_DQ_BY0_B3
NET 	 "cntrl0_DDR2_DQ[4]" 	 LOC = 	 "R27" ; 	 # DDR2_DIMM_DQ_BY0_B4
NET 	 "cntrl0_DDR2_DQ[5]" 	 LOC = 	 "R26" ; 	 # DDR2_DIMM_DQ_BY0_B5
NET 	 "cntrl0_DDR2_DQ[6]" 	 LOC = 	 "U28" ; 	 # DDR2_DIMM_DQ_BY0_B6
NET 	 "cntrl0_DDR2_DQ[7]" 	 LOC = 	 "U27" ; 	 # DDR2_DIMM_DQ_BY0_B7
NET 	 "cntrl0_DDR2_DQ[8]" 	 LOC = 	 "N29" ; 	 # DDR2_DIMM_DQ_BY1_B0
NET 	 "cntrl0_DDR2_DQ[9]" 	 LOC = 	 "M30" ; 	 # DDR2_DIMM_DQ_BY1_B1
NET 	 "cntrl0_DDR2_DQ[10]" 	 LOC = 	 "L30" ; 	 # DDR2_DIMM_DQ_BY1_B2
NET 	 "cntrl0_DDR2_DQ[11]" 	 LOC = 	 "J31" ; 	 # DDR2_DIMM_DQ_BY1_B3
NET 	 "cntrl0_DDR2_DQ[12]" 	 LOC = 	 "J30" ; 	 # DDR2_DIMM_DQ_BY1_B4
NET 	 "cntrl0_DDR2_DQ[13]" 	 LOC = 	 "G31" ; 	 # DDR2_DIMM_DQ_BY1_B5
NET 	 "cntrl0_DDR2_DQ[14]" 	 LOC = 	 "H30" ; 	 # DDR2_DIMM_DQ_BY1_B6
NET 	 "cntrl0_DDR2_DQ[15]" 	 LOC = 	 "L29" ; 	 # DDR2_DIMM_DQ_BY1_B7
NET 	 "cntrl0_DDR2_DQ[16]" 	 LOC = 	 "E31" ; 	 # DDR2_DIMM_DQ_BY2_B0
NET 	 "cntrl0_DDR2_DQ[17]" 	 LOC = 	 "F31" ; 	 # DDR2_DIMM_DQ_BY2_B1
NET 	 "cntrl0_DDR2_DQ[18]" 	 LOC = 	 "J29" ; 	 # DDR2_DIMM_DQ_BY2_B2
NET 	 "cntrl0_DDR2_DQ[19]" 	 LOC = 	 "H29" ; 	 # DDR2_DIMM_DQ_BY2_B3
NET 	 "cntrl0_DDR2_DQ[20]" 	 LOC = 	 "F30" ; 	 # DDR2_DIMM_DQ_BY2_B4
NET 	 "cntrl0_DDR2_DQ[21]" 	 LOC = 	 "G30" ; 	 # DDR2_DIMM_DQ_BY2_B5
NET 	 "cntrl0_DDR2_DQ[22]" 	 LOC = 	 "F29" ; 	 # DDR2_DIMM_DQ_BY2_B6
NET 	 "cntrl0_DDR2_DQ[23]" 	 LOC = 	 "E29" ; 	 # DDR2_DIMM_DQ_BY2_B7
NET 	 "cntrl0_DDR2_DQ[24]" 	 LOC = 	 "J32" ; 	 # DDR2_DIMM_DQ_BY3_B0
NET 	 "cntrl0_DDR2_DQ[25]" 	 LOC = 	 "F34" ; 	 # DDR2_DIMM_DQ_BY3_B1
NET 	 "cntrl0_DDR2_DQ[26]" 	 LOC = 	 "G33" ; 	 # DDR2_DIMM_DQ_BY3_B2
NET 	 "cntrl0_DDR2_DQ[27]" 	 LOC = 	 "E33" ; 	 # DDR2_DIMM_DQ_BY3_B3
NET 	 "cntrl0_DDR2_DQ[28]" 	 LOC = 	 "E32" ; 	 # DDR2_DIMM_DQ_BY3_B4
NET 	 "cntrl0_DDR2_DQ[29]" 	 LOC = 	 "E34" ; 	 # DDR2_DIMM_DQ_BY3_B5
NET 	 "cntrl0_DDR2_DQ[30]" 	 LOC = 	 "F33" ; 	 # DDR2_DIMM_DQ_BY3_B6
NET 	 "cntrl0_DDR2_DQ[31]" 	 LOC = 	 "G32" ; 	 # DDR2_DIMM_DQ_BY3_B7
NET 	 "cntrl0_DDR2_DQ[32]" 	 LOC = 	 "Y34" ; 	 # DDR2_DIMM_DQ_BY4_B0
NET 	 "cntrl0_DDR2_DQ[33]" 	 LOC = 	 "AA34" ; 	 # DDR2_DIMM_DQ_BY4_B1
NET 	 "cntrl0_DDR2_DQ[34]" 	 LOC = 	 "AA33" ; 	 # DDR2_DIMM_DQ_BY4_B2
NET 	 "cntrl0_DDR2_DQ[35]" 	 LOC = 	 "Y33" ; 	 # DDR2_DIMM_DQ_BY4_B3
NET 	 "cntrl0_DDR2_DQ[36]" 	 LOC = 	 "V34" ; 	 # DDR2_DIMM_DQ_BY4_B4
NET 	 "cntrl0_DDR2_DQ[37]" 	 LOC = 	 "W34" ; 	 # DDR2_DIMM_DQ_BY4_B5
NET 	 "cntrl0_DDR2_DQ[38]" 	 LOC = 	 "V33" ; 	 # DDR2_DIMM_DQ_BY4_B6
NET 	 "cntrl0_DDR2_DQ[39]" 	 LOC = 	 "V32" ; 	 # DDR2_DIMM_DQ_BY4_B7
NET 	 "cntrl0_DDR2_DQ[40]" 	 LOC = 	 "AP32" ; 	 # DDR2_DIMM_DQ_BY5_B0
NET 	 "cntrl0_DDR2_DQ[41]" 	 LOC = 	 "AN32" ; 	 # DDR2_DIMM_DQ_BY5_B1
NET 	 "cntrl0_DDR2_DQ[42]" 	 LOC = 	 "AN33" ; 	 # DDR2_DIMM_DQ_BY5_B2
NET 	 "cntrl0_DDR2_DQ[43]" 	 LOC = 	 "AN34" ; 	 # DDR2_DIMM_DQ_BY5_B3
NET 	 "cntrl0_DDR2_DQ[44]" 	 LOC = 	 "AM32" ; 	 # DDR2_DIMM_DQ_BY5_B4
NET 	 "cntrl0_DDR2_DQ[45]" 	 LOC = 	 "AM33" ; 	 # DDR2_DIMM_DQ_BY5_B5
NET 	 "cntrl0_DDR2_DQ[46]" 	 LOC = 	 "AL33" ; 	 # DDR2_DIMM_DQ_BY5_B6
NET 	 "cntrl0_DDR2_DQ[47]" 	 LOC = 	 "AL34" ; 	 # DDR2_DIMM_DQ_BY5_B7
NET 	 "cntrl0_DDR2_DQ[48]" 	 LOC = 	 "U31" ; 	 # DDR2_DIMM_DQ_BY6_B0
NET 	 "cntrl0_DDR2_DQ[49]" 	 LOC = 	 "U32" ; 	 # DDR2_DIMM_DQ_BY6_B1
NET 	 "cntrl0_DDR2_DQ[50]" 	 LOC = 	 "T34" ; 	 # DDR2_DIMM_DQ_BY6_B2
NET 	 "cntrl0_DDR2_DQ[51]" 	 LOC = 	 "U33" ; 	 # DDR2_DIMM_DQ_BY6_B3
NET 	 "cntrl0_DDR2_DQ[52]" 	 LOC = 	 "R32" ; 	 # DDR2_DIMM_DQ_BY6_B4
NET 	 "cntrl0_DDR2_DQ[53]" 	 LOC = 	 "R33" ; 	 # DDR2_DIMM_DQ_BY6_B5
NET 	 "cntrl0_DDR2_DQ[54]" 	 LOC = 	 "R34" ; 	 # DDR2_DIMM_DQ_BY6_B6
NET 	 "cntrl0_DDR2_DQ[55]" 	 LOC = 	 "T33" ; 	 # DDR2_DIMM_DQ_BY6_B7
NET 	 "cntrl0_DDR2_DQ[56]" 	 LOC = 	 "AF33" ; 	 # DDR2_DIMM_DQ_BY7_B0
NET 	 "cntrl0_DDR2_DQ[57]" 	 LOC = 	 "AB33" ; 	 # DDR2_DIMM_DQ_BY7_B1
NET 	 "cntrl0_DDR2_DQ[58]" 	 LOC = 	 "AC33" ; 	 # DDR2_DIMM_DQ_BY7_B2
NET 	 "cntrl0_DDR2_DQ[59]" 	 LOC = 	 "AB32" ; 	 # DDR2_DIMM_DQ_BY7_B3
NET 	 "cntrl0_DDR2_DQ[60]" 	 LOC = 	 "AC32" ; 	 # DDR2_DIMM_DQ_BY7_B4
NET 	 "cntrl0_DDR2_DQ[61]" 	 LOC = 	 "AD34" ; 	 # DDR2_DIMM_DQ_BY7_B5
NET 	 "cntrl0_DDR2_DQ[62]" 	 LOC = 	 "AC34" ; 	 # DDR2_DIMM_DQ_BY7_B6
NET 	 "cntrl0_DDR2_DQ[63]" 	 LOC = 	 "Y32" ; 	 # DDR2_DIMM_DQ_BY7_B7        

 


NET 	 "CLK200_N" 	 LOC = 	 "AH22" ; 	 # DIRECT_CLK_TO_FPGA2_N
NET 	 "CLK200_P" 	 LOC = 	 "AG22" ; 	 # DIRECT_CLK_TO_FPGA2_P
NET 	 "SYS_CLK_N" 	 LOC = 	 "AG13" ; 	 # EXT_CLK_TO_FPGA2_N
NET 	 "SYS_CLK_P" 	 LOC = 	 "AH12" ; 	 # EXT_CLK_TO_FPGA2_P

############################################################################ 

NET  "cntrl0_DDR2_DQ[*]"                                    IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_A[*]"                                     IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_BA[*]"                                    IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_RAS_N"                                    IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_CAS_N"                                    IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_WE_N"                                     IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_RESET_N"                                  IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_CS_N[*]"                                  IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_ODT[*]"                                   IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_CKE[*]"                                   IOSTANDARD = SSTL18_II;
NET  "cntrl0_DDR2_DM[*]"                                    IOSTANDARD = SSTL18_II;
NET  "SYS_CLK_P"                                     IOSTANDARD = LVPECL_25;
NET  "SYS_CLK_N"                                     IOSTANDARD = LVPECL_25;
NET  "CLK200_P"                                      IOSTANDARD = LVPECL_25;
NET  "CLK200_N"                                      IOSTANDARD = LVPECL_25;
NET  "cntrl0_DDR2_DQS[*]"                                   IOSTANDARD = DIFF_SSTL18_II_DCI;
NET  "cntrl0_DDR2_DQS_N[*]"                                   IOSTANDARD = DIFF_SSTL18_II_DCI;
//NET  "cntrl0_DDR2_DQS[*]"                                 IOSTANDARD = DIFF_SSTL18_II;
//NET  "cntrl0_DDR2_DQS_N[*]"                                 IOSTANDARD = DIFF_SSTL18_II;
NET  "cntrl0_DDR2_CK[*]"                                    IOSTANDARD = DIFF_SSTL18_II;
NET  "cntrl0_DDR2_CK_N[*]"                                  IOSTANDARD = DIFF_SSTL18_II;

############################################################################ 

# Clock constraints                                                        # 

############################################################################ 

NET "mem_clk_rst/SYS_CLK_IN" TNM_NET =  "SYS_CLK";									
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 2.7 ns HIGH 50 %;


############################################################################ 

# ############################################################################################
# More stuff added specific to DDR2 component simulation. Added by RChiu
# ############################################################################################

# Located in Bank 2 - VCCO2 = 2.5v
NET  "cntrl0_ERROR" 	 LOC = 	 "AD19";	        # Connect to FPGA2_LED0 (D14)
NET  "cntrl0_ERROR"      IOSTANDARD = LVCMOS25;
# Located in Bank 4 - VCCO4 = 2.5v. Appears to be active low (better be!)
NET  "SYS_RESET_IN" 	 LOC = 	 "AH14" ; 	     # Connect to FPGA2_RESET_N
NET  "SYS_RESET_IN" 	 IOSTANDARD = LVCMOS25;   # Connect to FPGA2_RESET_N

# For use with DIMM4
NET 	 "cntrl0_DDR2_CK_N[0]" 	 LOC = 	 "AK9" ; 	 # DDR2_DIMM5_CK0_N
NET 	 "cntrl0_DDR2_CK[0]" 	 LOC = 	 "AK8" ; 	 # DDR2_DIMM5_CK0_P
NET 	 "cntrl0_DDR2_CK_N[1]" 	 LOC = 	 "AJ11" ; 	 # DDR2_DIMM5_CK1_N
NET 	 "cntrl0_DDR2_CK[1]" 	 LOC = 	 "AK11" ; 	 # DDR2_DIMM5_CK1_P
NET 	 "cntrl0_DDR2_CK_N[2]" 	 LOC = 	 "AD11" ; 	 # DDR2_DIMM5_CK2_N
NET 	 "cntrl0_DDR2_CK[2]" 	 LOC = 	 "AD10" ; 	 # DDR2_DIMM5_CK2_P
NET 	 "cntrl0_DDR2_CKE[0]" 	 LOC = 	 "AG11" ; 	 # DDR2_DIMM5_CKE0
NET 	 "cntrl0_DDR2_CKE[1]" 	 LOC = 	 "AG10" ; 	 # DDR2_DIMM5_CKE1
NET 	 "cntrl0_DDR2_CS_N[0]" 	 LOC = 	 "W26" ; 	 # DDR2_DIMM5_CS0_N
NET 	 "cntrl0_DDR2_CS_N[1]" 	 LOC = 	 "Y26" ; 	 # DDR2_DIMM5_CS1_N
NET 	 "cntrl0_DDR2_ODT[0]" 	 LOC = 	 "AE11" ; 	 # DDR2_DIMM5_ODT0
NET 	 "cntrl0_DDR2_ODT[1]" 	 LOC = 	 "AF11" ; 	 # DDR2_DIMM5_ODT1

###############################################################################################################
# IDELAYCTRL Location Constraints
###############################################################################################################

INST "mem_io_ctrl/idelayctrl0" LOC = "IDELAYCTRL_X0Y4";
INST "mem_io_ctrl/idelayctrl1" LOC = "IDELAYCTRL_X0Y3";
INST "mem_io_ctrl/idelayctrl2" LOC = "IDELAYCTRL_X0Y2";