dds_iq_tap8.v

用verilog编写的高速8路并行dds模块

////////////////////////////////////////////////////
//
//  High Speed tap8 DDS for altera fpga
//  Using for connecting Ghz DA to synthesis wave
//
//  Coder: Yang Guojiang 
//  Copyright Jan 2009 Yangzhou Jinhao Elec S&T Ltd.
//  Version 1.0.2009.0114
///////////////////////////////////////////////////

`timescale  1ns / 1ns

module dds_acc
#(
	parameter ACCWIDTH = 32,
	parameter PHWIDTH  = 12
)
(
	clk,
	freq,
	fsign,
	ph,
	phclr,
	ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7,
	fso
);
	input clk;
	input [ACCWIDTH-1:0] freq;
	input fsign;
	input [PHWIDTH-1:0] ph;
	input phclr;
	output reg [PHWIDTH-1:0] ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7;
	output reg fso;
	

	reg [ACCWIDTH-4:0] facc;         //least 3 bits is "0" forever, so ignored
	reg [PHWIDTH-1:0] phoff;
	reg [ACCWIDTH-1:0] fd,fdd;
	reg [PHWIDTH-1:0] f3d,f3dd;
	reg [PHWIDTH-1:0] f5dd;
	reg [PHWIDTH-1:0] f6dd;
	reg [PHWIDTH-1:0] f7dd;
	
	reg fsd,fsdd;
	reg [PHWIDTH-1:0] phd;
	
	initial 
	   facc = 0; 

	//first dff	
	always @(posedge clk)
	begin
		if (phclr == 1'b1)
			facc <= {ACCWIDTH-3 {1'b0}};
		else 
			facc <= facc + freq[ACCWIDTH-4:0];
		fd <= freq;
		f3d <= freq[ACCWIDTH-1:ACCWIDTH-PHWIDTH] + freq[ACCWIDTH-2:ACCWIDTH-PHWIDTH-1];
		fsd <= fsign;
		phd <= ph;
	end

	//second dff
	always @(posedge clk)
	begin
		phoff <= facc[ACCWIDTH-4:ACCWIDTH-PHWIDTH-3] + phd;
		fdd   <= fd;
		f3dd  <= f3d;
		f5dd  <= f3d + fd[ACCWIDTH-2:ACCWIDTH-PHWIDTH-1];
		f6dd  <= fd[ACCWIDTH-3:ACCWIDTH-PHWIDTH-2] + fd[ACCWIDTH-2:ACCWIDTH-PHWIDTH-1];
		f7dd  <= f3d + fd[ACCWIDTH-3:ACCWIDTH-PHWIDTH-2];
		fsdd  <= fsd;
	end

	//third dff
	always @(posedge clk)
	begin
		ph0 <= phoff;
		ph1 <= phoff + fdd[ACCWIDTH-1:ACCWIDTH-PHWIDTH];
		ph2 <= phoff + fdd[ACCWIDTH-2:ACCWIDTH-PHWIDTH-1];
		ph3 <= phoff + f3dd;
		ph4 <= phoff + fdd[ACCWIDTH-3:ACCWIDTH-PHWIDTH-2];
		ph5 <= phoff + f5dd;
		ph6 <= phoff + f6dd;
		ph7 <= phoff + f7dd;
		fso <= fsdd;
	end
endmodule

module dds_sin_rom (
	address,
	clock,
	q);

	input	[9:0]  address;
	input	  clock;
	output	[7:0]  q;

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.clock0 (clock),
				.address_a (address),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_a ({8{1'b1}}),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_a (1'b0),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_a = "NONE",
		altsyncram_component.init_file = "dds_sin_rom.mif",
		altsyncram_component.intended_device_family = "Arria GX",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.operation_mode = "ROM",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "CLOCK0",
		altsyncram_component.ram_block_type = "M512",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_byteena_a = 1;


endmodule

module dds_cos_rom (
	address,
	clock,
	q);

	input	[9:0]  address;
	input	  clock;
	output	[7:0]  q;

	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];

	altsyncram	altsyncram_component (
				.clock0 (clock),
				.address_a (address),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_a ({8{1'b1}}),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_a (1'b1),
				.rden_b (1'b1),
				.wren_a (1'b0),
				.wren_b (1'b0));
	defparam
		altsyncram_component.address_aclr_a = "NONE",
		altsyncram_component.init_file = "dds_cos_rom.mif",
		altsyncram_component.intended_device_family = "Arria GX",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 1024,
		altsyncram_component.operation_mode = "ROM",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "CLOCK0",
		altsyncram_component.ram_block_type = "M512",
		altsyncram_component.widthad_a = 10,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_byteena_a = 1;


endmodule


module dds_sc_rom
#(
	parameter PHWIDTH  = 12,
	parameter OWIDTH   = 9
)
(
	clk,
	ph,
	fs,
	co,
	so
);
	input clk;
	input [PHWIDTH-1:0] ph;
	input fs;
	output reg [OWIDTH-1:0] co,so;

	wire [PHWIDTH-3:0] addr;
	wire [OWIDTH-2:0]  dc,ds;
	reg  sh,sl,shd,sld;
	reg  fsd,fsdd;
	
	assign addr = (ph[PHWIDTH-2] == 1'b1)?  (~ph[PHWIDTH-3:0]):(ph[PHWIDTH-3:0]);

	dds_sin_rom sin_rom(addr,clk,ds);
	dds_cos_rom cos_rom(addr,clk,dc);
	always @(posedge clk)
	begin
		fsd <= fs;
		sh  <= ph[PHWIDTH-1];
		sl  <= ph[PHWIDTH-2];
		
		fsdd <= fsd;
		shd <= sh;
		sld <= sl;
	end	

	always @(posedge clk)
	begin
		co  <= (shd == sld)?  {1'b0, dc} : {1'b1, ~dc};
		so  <= (shd == fsdd)?  {1'b0, ds} : {1'b1, ~ds};
	end

endmodule

	
module dds_iq_tap8
#(
	parameter ACCWIDTH = 32,
	parameter PHWIDTH  = 12,
	parameter OWIDTH   = 9
)
(
	clk,
	freq,
	fsign,
	ph,
	phclr,
	c0,c1,c2,c3,c4,c5,c6,c7,
	s0,s1,s2,s3,s4,s5,s6,s7
);

	input clk;
	input [ACCWIDTH-1:0] freq;
	input fsign;
	input [PHWIDTH-1:0] ph;
	input phclr;
	output [OWIDTH-1:0] c0,c1,c2,c3,c4,c5,c6,c7;
	output [OWIDTH-1:0] s0,s1,s2,s3,s4,s5,s6,s7;
	
	wire [PHWIDTH-1:0] ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7;
	wire fso;
	
	dds_acc #(.ACCWIDTH(ACCWIDTH),.PHWIDTH(PHWIDTH)) dds_acc_inst  
	(
		clk,
		freq,
		fsign,
		ph,
		phclr,
		ph0,ph1,ph2,ph3,ph4,ph5,ph6,ph7,
		fso
	);

	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom0 (clk, ph0, fso, c0, s0);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom1 (clk, ph1, fso, c1, s1);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom2 (clk, ph2, fso, c2, s2);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom3 (clk, ph3, fso, c3, s3);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom4 (clk, ph4, fso, c4, s4);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom5 (clk, ph5, fso, c5, s5);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom6 (clk, ph6, fso, c6, s6);
	dds_sc_rom #(.PHWIDTH(PHWIDTH), .OWIDTH(OWIDTH)) dds_sc_rom7 (clk, ph7, fso, c7, s7);
	
	
endmodule