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FPGA 的代码
uart.mrp
Release 7.1.01i Map H.39
Xilinx Mapping Report File for Design 'uart'
Design Information
------------------
Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_FPGA.ise -int
ram_control.cr.mti
{E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/cyclone_atoms.v} {1 {vlog -work work -vlog01compat {E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/c
ram_control.cr.mti
{E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/cyclone_atoms.v} {1 {vlog -work work -vlog01compat {E:/farsight_fpga_course/code/high/onchip ram/quartus/simulation/modelsim/c
uar_sm.v
//*****************************************************************************************//
// Project : FPGA based Digital Design using Verilog HDL
// File : uar_sm.v
// Autho
uat_sm.v
//*****************************************************************************************//
// Project : FPGA based Digital Design using Verilog HDL
// File : uat_sm.v
// Au
uar_top.v
//*****************************************************************************************//
// Project : FPGA based Digital Design using Verilog HDL
// File : uar_top.v
// Auth
fpgaloading.c
/*******************************************************************************
** Filename: FPGALoading.c
** Author: Zhoudan
** Description: Use GPIO or SPI to Loading FPGA Program
** Da
netlist.lst
R:\training\training\desperf\labs\fpga_editor\correlate_and_accumulate.ngc 1132023826
OK
fpgaloading.c
/*******************************************************************************
** Filename: FPGALoading.c
** Author: Zhoudan
** Description: Use GPIO or SPI to Loading FPGA Program
** Da
runxst_tcl.rsp
set allSynthModules {serial.MOD diag.MOD fpga_40RS232.MOD}