uar_sm.v

it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : uar_sm.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

module uar_sm(// Inputs
              clk_16x,
              rst_n,
              din_rdy,
              shift_count,
              count_sample,
              // Outputs
              start_bit_sig,
              data_bits_sig,
              stop_bit_sig
             );  
// Inputs
input       clk_16x ;
input       rst_n ;
input       din_rdy ;
input [3:0] shift_count ;
input [3:0] count_sample;
// Outputs
output      start_bit_sig ;
output      data_bits_sig ;
output      stop_bit_sig ;

parameter [3:0] IDLE          = 4'b0001 ;
parameter [3:0] START_BIT_ST  = 4'b0010 ;
parameter [3:0] DATA_BITS_ST  = 4'b0100 ;
parameter [3:0] STOP_BIT_ST   = 4'b1000 ;

// Register and Wire Declaration 
reg       start_bit_sig ;
reg       data_bits_sig ;
reg       stop_bit_sig ;
reg [3:0] rx_state ;

// State Register, Next State & Output Logic
always @(posedge clk_16x or negedge rst_n)
begin
  if(~rst_n) begin
     rx_state <= #1 IDLE ;
  end 
  else begin
    case(rx_state)
        IDLE         : begin
                          if(din_rdy)
                             rx_state <= #1 START_BIT_ST ;
                          else     
                             rx_state <= #1 IDLE ;
                       end
         START_BIT_ST : begin
			   if(shift_count == 4'd1)
                              rx_state <= #1 DATA_BITS_ST ;
                           else     
                              rx_state <= #1 START_BIT_ST ;
                        end
         DATA_BITS_ST : begin
			   if(shift_count == 4'd9)
                              rx_state <= #1 STOP_BIT_ST ;
                           else     
                              rx_state <= #1 DATA_BITS_ST ;
                        end
         STOP_BIT_ST  : begin
			   if(count_sample == 4'd9)
                              rx_state <= #1 IDLE ;
                           else     
                              rx_state <= #1 STOP_BIT_ST ;
                        end     
         default      : begin
                           rx_state <= #1 IDLE ;
                        end   
      endcase
   end   
end

always @(rx_state)
begin
   case(rx_state)
      IDLE         : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b0 ;
                     end
      START_BIT_ST : begin
                        start_bit_sig = 1'b1 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b0 ;
                     end
      DATA_BITS_ST : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b1 ;
                        stop_bit_sig = 1'b0 ;
                     end
      STOP_BIT_ST  : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b1 ;
                     end     
      default      : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b0 ;
                     end   
   endcase
end

endmodule