uat_sm.v

it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : uat_sm.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

module uat_sm(// Inputs
              clk_x,
              rst_n,
              din_rdy,
              shift_count,
              // Outputs
              start_bit_sig,
              data_bits_sig,
              stop_bit_sig   
             );  

input       clk_x ;
input       rst_n ;
input       din_rdy ;
input [2:0] shift_count ;
output      start_bit_sig ;
output      data_bits_sig ;
output      stop_bit_sig ;

parameter [3:0] IDLE          = 4'b0001 ;
parameter [3:0] START_BIT_ST  = 4'b0010 ;
parameter [3:0] DATA_BITS_ST  = 4'b0100 ;
parameter [3:0] STOP_BIT_ST   = 4'b1000 ;

reg       start_bit_sig ;
reg       data_bits_sig ;
reg       stop_bit_sig ;
reg [3:0] tx_state ;


always @(posedge clk_x or negedge rst_n)
begin
   if(~rst_n) begin
      tx_state <= #1 4'd0 ;
   end
   else begin
      case(tx_state)
         IDLE         : begin
                           if(din_rdy)
                              tx_state <= #1 START_BIT_ST;
                           else
                              tx_state <= #1 IDLE;
                        end
         START_BIT_ST : begin
                           tx_state <= #1 DATA_BITS_ST;
                        end      
         DATA_BITS_ST : begin
                           if(shift_count == 3'd7)
                              tx_state <= #1 STOP_BIT_ST;
                           else     
                              tx_state <= #1 DATA_BITS_ST;
                        end      
         STOP_BIT_ST  : begin
                           if(din_rdy)
                              tx_state <= #1 START_BIT_ST;
                           else     
                              tx_state <= #1 IDLE;
                        end
         default      : begin
                           tx_state <= #1 IDLE ;
                        end   
      endcase
   end      
end

always @(tx_state)
begin
   case(tx_state)
      IDLE         : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b0 ;
                     end
      START_BIT_ST : begin
                        start_bit_sig = 1'b1 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b0 ;
                     end      
      DATA_BITS_ST : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b1 ;
                        stop_bit_sig = 1'b0 ;
                     end      
      STOP_BIT_ST  : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b1 ;
                     end
      default      : begin
                        start_bit_sig = 1'b0 ;
                        data_bits_sig = 1'b0 ;
                        stop_bit_sig = 1'b0 ;
                     end   
   endcase
end

endmodule