代码搜索：FPGA
找到约 10,000 项符合「FPGA」的源代码
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vwf fpga_dsp_portlink.sim.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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hdb fpga_dsp_portlink.map.hdb
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cdb fpga_dsp_portlink.signalprobe.cdb
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rdb fpga_dsp_portlink.sim.rdb
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qmsg fpga_dsp_portlink.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
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qrpt fpga_dsp_portlink.sim.qrpt
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qmsg fpga_dsp_portlink.fnsim.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
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rpt fpga_dsp_portlink.map.rpt
Analysis & Synthesis report for FPGA_DSP_PortLink
Thu Jan 03 11:09:21 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
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bsf fpga_dsp_portlink_inner.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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vhd fpga_dsp_portlink11.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FPGA_DSP_PortLink11 IS
GENERIC(
--ADDR_FromDSP_WIDTH : INTEGER := 2;
DATA_FromToDSP_WIDTH : INTEGER := 16;
FIFO_StatusWord_WID