fpga_dsp_portlink11.vhd

implemention of FPGA and DSP linking port, using Asynchronous mode

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FPGA_DSP_PortLink11 IS
	GENERIC(
				--ADDR_FromDSP_WIDTH			:	INTEGER	:=	2;
				DATA_FromToDSP_WIDTH		:	INTEGER	:=	16;
				FIFO_StatusWord_WIDTH		:	INTEGER	:=	16;
				FIFO_LENGTH					:	INTEGER	:=	256
			);
	PORT(
			--CS_FromDSP			:	IN		STD_LOGIC;
			CLK0				:	IN		STD_LOGIC;
			CLK1				:	IN		STD_LOGIC;
			--ADDR_FromDSP		:	IN		STD_LOGIC_VECTOR(ADDR_FromDSP_WIDTH-1 DOWNTO 0);
			DATA_FromDSP		:	IN		STD_LOGIC_VECTOR(DATA_FromToDSP_WIDTH-1 DOWNTO 0);
			DATA_From_Inner		:	IN		STD_LOGIC_VECTOR(DATA_FromToDSP_WIDTH-1 DOWNTO 0);
			DATA_ToDSP			:	OUT		STD_LOGIC_VECTOR(DATA_FromToDSP_WIDTH-1 DOWNTO 0);
			DATA_ToAD9858		:	OUT		STD_LOGIC_VECTOR(FIFO_StatusWord_WIDTH-1 DOWNTO 0);
			FIFO_W_ByDSP_STATUS	:	OUT		STD_LOGIC_VECTOR(FIFO_StatusWord_WIDTH-1 DOWNTO 0);
			FIFO_R_ByDSP_STATUS	:	OUT		STD_LOGIC_VECTOR(FIFO_StatusWord_WIDTH-1 DOWNTO 0);
			CLKOUT				:	OUT		STD_LOGIC
		);
END FPGA_DSP_PortLink11;

ARCHITECTURE FPGA_DSP_PortLink_ARC OF FPGA_DSP_PortLink11 IS
	TYPE FIFO_Type	IS	ARRAY(0 TO FIFO_LENGTH-1) OF STD_LOGIC_VECTOR(DATA_FromToDSP_WIDTH-1 DOWNTO 0);
	SUBTYPE CounterType_For_FIFO_Status IS INTEGER RANGE 0 TO FIFO_LENGTH;
	SIGNAL FIFO_W_ByDSP : FIFO_Type;
	SIGNAL FIFO_R_ByDSP : FIFO_Type;
	SIGNAL Counter_For_FIFO_W_ByDSP : CounterType_For_FIFO_Status := 0;
	SIGNAL Counter_For_FIFO_R_ByDSP : CounterType_For_FIFO_Status := 0;
	--component PLL0
	--PORT
	--(
	--	inclk0		: IN STD_LOGIC  := '0';
	--	pllena		: IN STD_LOGIC  := '1';
	--	c0		: OUT STD_LOGIC 
	--);
	--end component;

BEGIN
	--PLL0_inst : PLL0 PORT MAP (
	--	inclk0	 => CLKIN,
	--	pllena	 => CS_FromDSP,
	--	c0	 => CLK_Wire
	--);
	
	CLKOUT <= CLK0;
	
	PROCESS(CLK0)
	BEGIN
		IF(CLK0'EVENT AND CLK0='0')THEN
			--CASE ADDR_FromDSP IS
				--WHEN "00" => NULL;
				--WHEN "01" =>
				--	__statement;
				--WHEN "10" =>
					IF(Counter_For_FIFO_R_ByDSP > 0 AND Counter_For_FIFO_R_ByDSP <= FIFO_LENGTH)THEN
						DATA_ToDSP <= FIFO_R_ByDSP(0);
						FIFO_R_ByDSP(0 TO FIFO_LENGTH-2) <= FIFO_R_ByDSP(1 TO FIFO_LENGTH-1);	
						FIFO_R_ByDSP(FIFO_LENGTH-1) <= (OTHERS => '0');	
						Counter_For_FIFO_R_ByDSP <= Counter_For_FIFO_R_ByDSP - 1;	
					ELSE
						DATA_ToDSP <= (OTHERS => '0');
						Counter_For_FIFO_R_ByDSP <= 0;
					END IF;
				--WHEN "01" =>
				--WHEN "11" =>
				--	__statement;
				--WHEN OTHERS =>
				--	NULL;
			--END CASE;
		END IF;

		IF(CLK0'EVENT AND CLK0='1')THEN
			IF(Counter_For_FIFO_R_ByDSP >= 0 AND Counter_For_FIFO_R_ByDSP < FIFO_LENGTH)THEN
				FIFO_R_ByDSP(Counter_For_FIFO_R_ByDSP) <= DATA_From_Inner; 
				Counter_For_FIFO_R_ByDSP <= Counter_For_FIFO_R_ByDSP + 1;
			ELSE 
				FIFO_R_ByDSP(0 TO FIFO_LENGTH-2) <= FIFO_R_ByDSP(1 TO FIFO_LENGTH-1);
				FIFO_R_ByDSP(FIFO_LENGTH-1) <= DATA_From_Inner;
				Counter_For_FIFO_R_ByDSP <= FIFO_LENGTH	;
			END IF;
		END IF;

	END PROCESS;

	PROCESS(CLK1)
	BEGIN
		IF(CLK1'EVENT AND CLK1='1')THEN
			--CASE ADDR_FromDSP IS
				--WHEN "00" => NULL;
				--WHEN "01" =>
				--	__statement;
				--WHEN "10" =>
					IF(Counter_For_FIFO_W_ByDSP > 0 AND Counter_For_FIFO_W_ByDSP <= FIFO_LENGTH)THEN
						DATA_ToAD9858 <= FIFO_W_ByDSP(0);
						FIFO_W_ByDSP(0 TO FIFO_LENGTH-2) <= FIFO_W_ByDSP(1 TO FIFO_LENGTH-1);	
						FIFO_W_ByDSP(FIFO_LENGTH-1) <= (OTHERS => '0');	
						Counter_For_FIFO_R_ByDSP <= Counter_For_FIFO_R_ByDSP - 1;	
					ELSE
						DATA_ToAD9858 <= (OTHERS => '0');
						Counter_For_FIFO_R_ByDSP <= 0;
					END IF;
				--WHEN "01" =>
				--WHEN "11" =>
				--	__statement;
				--WHEN OTHERS =>
				--	NULL;
			--END CASE;
		END IF;
		
		IF(CLK1'EVENT AND CLK1='0')THEN
			IF(Counter_For_FIFO_W_ByDSP >= 0 AND Counter_For_FIFO_W_ByDSP < FIFO_LENGTH)THEN
				FIFO_W_ByDSP(Counter_For_FIFO_W_ByDSP) <= DATA_FromDSP; 
				Counter_For_FIFO_W_ByDSP <= Counter_For_FIFO_W_ByDSP + 1;
			ELSE 
				FIFO_W_ByDSP(0 TO FIFO_LENGTH-2) <= FIFO_W_ByDSP(1 TO FIFO_LENGTH-1);
				FIFO_W_ByDSP(FIFO_LENGTH-1) <= DATA_FromDSP;
				Counter_For_FIFO_W_ByDSP <= FIFO_LENGTH	;
			END IF;
		END IF;
		
	END PROCESS;	

END FPGA_DSP_PortLink_ARC;