fpga_dsp_portlink.map.rpt

implemention of FPGA and DSP linking port, using Asynchronous mode

Analysis & Synthesis report for FPGA_DSP_PortLink
Thu Jan 03 11:09:21 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. User-Specified and Inferred Latches
  9. General Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component
 12. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated
 13. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram
 14. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|altsyncram_ofr:fifo_ram|altsyncram_uk61:altsyncram3
 15. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp
 16. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_hv7:rs_dgwp|dffpipe_b09:dffpipe5
 17. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp
 18. Source assignments for FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component|dcfifo_fe71:auto_generated|alt_synch_pipe_iv7:ws_dgrp|dffpipe_c09:dffpipe8
 19. Parameter Settings for User Entity Instance: lpm_bustri1:inst4|lpm_bustri:lpm_bustri_component
 20. Parameter Settings for User Entity Instance: FIFO_RDN_ByDSP:inst5|dcfifo:dcfifo_component
 21. dcfifo Parameter Settings by Entity Instance
 22. Analysis & Synthesis Equations
 23. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Jan 03 11:09:21 2008    ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name                      ; FPGA_DSP_PortLink                        ;
; Top-level Entity Name              ; FPGA_DSP_PortLink_BiBus_oneFIFO          ;
; Family                             ; Cyclone II                               ;
; Total combinational functions      ; 77                                       ;
; Total registers                    ; 103                                      ;
; Total pins                         ; 21                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 32,768                                   ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                             ;
+--------------------------------------------------------------------+---------------------------------+--------------------+
; Option                                                             ; Setting                         ; Default Value      ;
+--------------------------------------------------------------------+---------------------------------+--------------------+
; Device                                                             ; EP2C8Q208C7                     ;                    ;
; Top-level entity name                                              ; FPGA_DSP_PortLink_BiBus_oneFIFO ; FPGA_DSP_PortLink  ;
; Family name                                                        ; Cyclone II                      ; Stratix            ;
; Use smart compilation                                              ; Off                             ; Off                ;
; Restructure Multiplexers                                           ; Auto                            ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                             ; Off                ;
; Preserve fewer node names                                          ; On                              ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                             ; Off                ;
; Verilog Version                                                    ; Verilog_2001                    ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93                          ; VHDL93             ;
; State Machine Processing                                           ; Auto                            ; Auto               ;
; Extract Verilog State Machines                                     ; On                              ; On                 ;
; Extract VHDL State Machines                                        ; On                              ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                              ; On                 ;
; DSP Block Balancing                                                ; Auto                            ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                              ; -1                 ;
; NOT Gate Push-Back                                                 ; On                              ; On                 ;
; Power-Up Don't Care                                                ; On                              ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                             ; Off                ;
; Remove Duplicate Registers                                         ; On                              ; On                 ;
; Ignore CARRY Buffers                                               ; Off                             ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                             ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                             ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                             ; Off                ;
; Ignore LCELL Buffers                                               ; Off                             ; Off                ;
; Ignore SOFT Buffers                                                ; On                              ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                             ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced                        ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                              ; 70                 ;
; Auto Carry Chains                                                  ; On                              ; On                 ;
; Auto Open-Drain Pins                                               ; On                              ; On                 ;
; Remove Duplicate Logic                                             ; On                              ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                             ; Off                ;
; Perform gate-level register retiming                               ; Off                             ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                              ; On                 ;
; Auto ROM Replacement                                               ; On                              ; On                 ;
; Auto RAM Replacement                                               ; On                              ; On                 ;
; Auto Shift Register Replacement                                    ; On                              ; On                 ;
; Auto Clock Enable Replacement                                      ; On                              ; On                 ;
; Allow Synchronous Control Signals                                  ; On                              ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                             ; Off                ;
; Auto Resource Sharing                                              ; Off                             ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                             ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                             ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                             ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; -1                              ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                             ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                              ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                             ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                               ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation              ; Normal compilation ;
; HDL message level                                                  ; Level2                          ; Level2             ;
+--------------------------------------------------------------------+---------------------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                     ;
+-------------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+
; File Name with User-Entered Path    ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                  ;
+-------------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+
; lpm_bustri1.vhd                     ; yes             ; User VHDL File                     ; E:/ADFM/FPGA_DSP_PortLink/lpm_bustri1.vhd                                     ;
; FIFO_RDN_ByDSP.vhd                  ; yes             ; User VHDL File                     ; E:/ADFM/FPGA_DSP_PortLink/FIFO_RDN_ByDSP.vhd                                  ;