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FPGA 的代码
fpgaload.c
/*******************************************************************************
版权所有 (C), 2005, 上海中兴通讯技术有限责任公司
********************************************************************************
key_scan.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
virtex.c
/*!***************************************************************************
*!
*! FILE NAME : vertex.c
*!
*! DESCRIPTION: Implements an interface towards virtex FPGA (mounted on one of our
*!
virtex.c
/*!***************************************************************************
*!
*! FILE NAME : vertex.c
*!
*! DESCRIPTION: Implements an interface towards virtex FPGA (mounted on one of our
*!
virtex.c
/*!***************************************************************************
*!
*! FILE NAME : vertex.c
*!
*! DESCRIPTION: Implements an interface towards virtex FPGA (mounted on one of our
*!
stdout.log
Starting: D:\Program\FPGA_software\Synplicity\fpga_8804\bin\mbin\synplify.exe
Install: D:\Program\FPGA_software\Synplicity\fpga_8804
Date: Fri Jun 06 17:01:02 2008
Version: 8.8.
virtex.c
/*!***************************************************************************
*!
*! FILE NAME : vertex.c
*!
*! DESCRIPTION: Implements an interface towards virtex FPGA (mounted on one of our
*!
yucca.c
/*
* arch/ppc/platforms/4xx/yucca.c
*
* Yucca board specific routines
*
* Roland Dreier (based on luan.c by Matt Porter)
*
* Copyright 2004-2005 MontaVista Software Inc.
*
controlpath.v
module ControlPath(
Clk, //Clock
Reset, //Clear Control Path State
Control_R_W, //Control_R_W = 0 ==> FPGA to PC,
//Control_R_W = 1 ==> PC to FPGA,
PC_Check_1, //PC_Check_1 =
bit_add.prm
PROMGEN: Xilinx Prom Generator G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
promgen -w -p mcs -c FF -o g:\vijay_kumar\vijay_vhdl6sem_e&elab\vhdl_lab_6seme&e_poly\fpga_programs\fp