stdout.log

来自「使用VERILOG实现QPSK信号的匹配滤波」· LOG 代码 · 共 19 行

Starting:    D:\Program\FPGA_software\Synplicity\fpga_8804\bin\mbin\synplify.exe
Install:     D:\Program\FPGA_software\Synplicity\fpga_8804
Date:        Fri Jun 06 17:01:02 2008
Version:     8.8.0.4


Arguments:   -pro match_rec.prj match_rec.srs
ProductType: synplify_pro

License checkout: synplifypro
License: synplifypro node-locked 



exit status=0