key_scan.map.qmsg

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Aug 10 17:48:29 2005 " "Info: Processing started: Wed Aug 10 17:48:29 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off KEY_SCAN -c KEY_SCAN " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off KEY_SCAN -c KEY_SCAN" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_scan_lie.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file key_scan_lie.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 key_scan_lie " "Info: Found entity 1: key_scan_lie" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pailie.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pailie.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pailie-rtl " "Info: Found design unit 1: pailie-rtl" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pailie " "Info: Found entity 1: pailie" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Keyboard.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Keyboard.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Keyboard-Scan " "Info: Found design unit 1: Keyboard-Scan" {  } { { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Keyboard " "Info: Found entity 1: Keyboard" {  } { { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fpga_s51_0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fpga_s51_0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FPGA_S51_0-behav " "Info: Found design unit 1: FPGA_S51_0-behav" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 FPGA_S51_0 " "Info: Found entity 1: FPGA_S51_0" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Keyboard inst " "Warning: Block or symbol \"Keyboard\" of instance \"inst\" overlaps another block or symbol" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 96 184 360 224 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } { 48 328 496 64 "p\[7..0\]" "" } } } }  } 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } { 192 784 960 208 "P0\[7..0\]" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b pailie.vhd(33) " "Warning: VHDL Process Statement warning at pailie.vhd(33): signal \"b\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data\[7\] pailie.vhd(16) " "Warning: Tied undriven net \"data\[7\]\" at pailie.vhd(16) to GND or VCC" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data\[6\] pailie.vhd(16) " "Warning: Tied undriven net \"data\[6\]\" at pailie.vhd(16) to GND or VCC" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data\[5\] pailie.vhd(16) " "Warning: Tied undriven net \"data\[5\]\" at pailie.vhd(16) to GND or VCC" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "data\[4\] pailie.vhd(16) " "Warning: Tied undriven net \"data\[4\]\" at pailie.vhd(16) to GND or VCC" {  } { { "pailie.vhd" "" { Text "F:/EDA/KEY_SCAN/pailie.vhd" 16 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[7\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[7\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[7\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[7\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[6\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[6\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[6\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[6\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[5\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[5\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[5\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[5\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[4\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[4\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[4\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[4\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[3\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[3\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[3\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[3\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[2\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[2\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[2\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[2\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[1\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[1\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}