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FPGA 的代码
fpga_core.areasrr
----------------------------------------------------------------------
Report for cell fpga_core.verilog
Cell usage:
cell
fpga_core.edn
(edif fpga_core
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2008 5 7 16 22 48)
(author "Synplicity, Inc.")
(progra
fpga_core.srm
@E"VRMNFMl;C"RHyVDjCR
"VROD:\HsLCF$\#MHbDV#$\$DMbH_V$U4UN\LDH\FbsNO#H\FbsNO#Hd"3P;VRyHRDC4R
V"\E:VNbo_#0C0b\VoVN_H_VFj.4._\j.#slN0MoC\VVHFb_Vo.N4UUjG\VVHFb_Vo.N4UUjG3;P"RHyVD.CR
"VREV:\b_oN00C#\oVb
fpga_core.tlg
Selecting top level module fpga_core
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1705:7:1705:9|Synthesizing module VCC
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\pro
fpga_core.srd
f "noname"; #file 0
f "c:\libero\synplify\synplify_88a1\lib\proasic\proasic3.v"; #file 1
f "h:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v"; #file 2
f "h:\fpga_test\fpga_
fpga_core.srr
#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: ZHOUHUAGOU
#Implementation: synthesis
#Thu Jan 17 15:33:39 2008
$
fpga_core.tcl
# Created by Libero Project Manager 8.0.0.40
# Fri May 16 15:09:12 2008
# (NEW DESIGN)
# create a new design
new_design -name "fpga_core" -family "ProASIC3" -block "ON"
# set default back-a
fpga-test.c
/*
fpga-test.c, need insmod s3c2410-fpga.o first.
author: wb
date: 2005-6-13 21:05
*/
#include
#include
#include
#include