fpga_core.tcl

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# Created by Libero Project Manager 8.0.0.40
# Fri May 16 15:09:12 2008

# (NEW DESIGN)

# create a new design
new_design -name "fpga_core" -family "ProASIC3" -block "ON"

# set default back-annotation base-name
set_defvar "BA_NAME" "fpga_core_ba"

# set working directory
set_defvar "DESDIR" "H:/fpga_test/fpga_fifo_0122_02/designer/impl2"

# set back-annotation output directory
set_defvar "BA_DIR" "H:/fpga_test/fpga_fifo_0122_02/designer/impl2"

# enable the export back-annotation netlist
set_defvar "BA_NETLIST_ALSO" "1"

# set EDIF options
set_defvar "EDNINFLAVOR" "GENERIC"

# set HDL options
set_defvar "NETLIST_NAMING_STYLE" "VERILOG"

# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
set_defvar "EXPORT_STATUS_REPORT_FILENAME" "fpga_core.rpt"

# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
set_defvar "AUDIT_DCF_FILE" "1"
set_defvar "AUDIT_PIN_FILE" "1"
set_defvar "AUDIT_ADL_FILE" "1"

# import of input files
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VERILOG" {../../synthesis/fpga_core.edn} \
-format "sdc"  {..\..\synthesis\fpga_core_sdc.sdc}

# export translation of original netlist
export -format "verilog" {../../synthesis/fpga_core.v}