fpga_core.srr

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: ZHOUHUAGOU

#Implementation: synthesis

#Thu Jan 17 15:33:39 2008

$ Start of Compile
#Thu Jan 17 15:33:39 2008

Synplicity Verilog Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@I::"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v"
@I::"H:\fpga_test\test\new\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v"
@I::"H:\fpga_test\test\new\hdl\fifo_fpga_1280X8.v"
@E: CG501 :"H:\fpga_test\test\new\hdl\fifo_fpga_1280X8.v":42:4:42:6|Expecting delimiter: , or ; or )
@E: CG342 :"H:\fpga_test\test\new\hdl\fifo_fpga_1280X8.v":89:8:89:12|Expecting target variable, got state - Misspelling?
@E: CG342 :"H:\fpga_test\test\new\hdl\fifo_fpga_1280X8.v":98:8:98:12|Expecting target variable, got ctrl1 - Misspelling?
@E: CG100 :"H:\fpga_test\test\new\hdl\fifo_fpga_1280X8.v":159:10:159:14|Reference to unknown variable state
@E: CS187 :"H:\fpga_test\test\new\hdl\fifo_fpga_1280X8.v":205:4:205:6|Expecting endmodule
5 syntax errors
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jan 17 15:33:40 2008

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