fpga_core.areasrr
来自「可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除6」· AREASRR 代码 · 共 83 行
AREASRR
83 行
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Report for cell fpga_core.verilog
Cell usage:
cell count area count*area
AND2 2 1.0 2.0
AND3 7 1.0 7.0
AO1B 1 1.0 1.0
AO1C 2 1.0 2.0
AO1D 1 1.0 1.0
AOI1 1 1.0 1.0
AOI1B 1 1.0 1.0
AX1C 1 1.0 1.0
AX1E 2 1.0 2.0
DFN1C0 20 1.0 20.0
DFN1E0P0 1 1.0 1.0
DFN1E1C0 2 1.0 2.0
DFN1P0 5 1.0 5.0
GND 1 0.0 0.0
INV 4 1.0 4.0
NOR2 5 1.0 5.0
NOR2A 15 1.0 15.0
NOR2B 4 1.0 4.0
NOR3 1 1.0 1.0
NOR3A 8 1.0 8.0
NOR3B 2 1.0 2.0
NOR3C 2 1.0 2.0
OA1 1 1.0 1.0
OA1C 2 1.0 2.0
OAI1 1 1.0 1.0
OR2A 4 1.0 4.0
OR2B 9 1.0 9.0
OR3A 1 1.0 1.0
OR3B 1 1.0 1.0
TRIBUFF 16 0.0 0.0
VCC 1 0.0 0.0
XA1 3 1.0 3.0
XA1A 1 1.0 1.0
XAI1 1 1.0 1.0
XNOR2 2 1.0 2.0
XOR2 8 1.0 8.0
fifo_fpga1280x8 1 680.0 680.0
TOTAL 140 801.0
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Report for cell fifo_fpga1280x8.netlist
Instance path: fifo_data_inst
Cell usage:
cell count area count*area
AND2 55 1.0 55.0
AND2A 3 1.0 3.0
AND3 17 1.0 17.0
AO1 59 1.0 59.0
AO1C 7 1.0 7.0
AOI1 2 1.0 2.0
BUFF 4 1.0 4.0
DFN1 2 1.0 2.0
DFN1C0 91 1.0 91.0
DFN1E1C0 39 1.0 39.0
DFN1P0 1 1.0 1.0
GND 1 0.0 0.0
INV 1 1.0 1.0
MAJ3 19 1.0 19.0
MX2 32 1.0 32.0
NAND2 2 1.0 2.0
NAND3A 14 1.0 14.0
NOR2 2 1.0 2.0
NOR2A 18 1.0 18.0
NOR3 1 1.0 1.0
NOR3A 7 1.0 7.0
OA1A 1 1.0 1.0
OA1C 1 1.0 1.0
OR2 2 1.0 2.0
OR2A 24 1.0 24.0
OR3 2 1.0 2.0
RAM512X18 3 0.0 0.0
VCC 1 0.0 0.0
XNOR2 70 1.0 70.0
XNOR3 37 1.0 37.0
XOR2 133 1.0 133.0
XOR3 34 1.0 34.0
TOTAL 685 680.0
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