代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/164962/10080324
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/164962/10080387
txt pelian_contrller.txt
-- Pelican Crossing Controller
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity pelcross is
port(clock, reset, pedestrian : in std_logic;
www.eeworm.com/read/353811/10416426
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/353811/10416468
txt 带莫尔_米勒输出的状态机.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/351504/10645192
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/417397/10991747
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/417397/10991750
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/439407/6932052
vhd cam_top.vhd
--
-- Module: CAM_Top / Top Level
-- Design: CAM_Top
-- VHDL code: Hierarchical wrapper
-- Instantiate CAM_generic_8s (depth variable by 16x8bits word)
--
-- Synthesis Synopsys FPGA Express v
www.eeworm.com/read/439407/6932085
v init_8_ram16x1s.v
//
// Module: INIT_8_RAM16x1s
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.3
// Enable Synthesis Option: Verilog Pre-pro
www.eeworm.com/read/439407/6932090
v init_ramb4_s1_s16.v
//
// Module: INIT_RAMB4_S1_S16
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.3
// Enable Synthesis Option: Verilog Pre-p