代码搜索：FPGA加速

找到约 10,000 项符合「FPGA加速」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/10793/190772

mti uart.cr.mti

F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
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www.eeworm.com/read/17491/732662

mti uart.cr.mti

F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v {2 {vlog -work work -vopt F:/EdaOk/project/PeriphDIY/uart/fpga/V0p10/src/rxd.v Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
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www.eeworm.com/read/17670/752774

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high
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www.eeworm.com/read/17694/754232

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol
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www.eeworm.com/read/17694/754235

regkeys

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -w -intstyle ise -ol std -t 1 DDR_TX_TEST_map.ncd DDR_TX_TE
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www.eeworm.com/read/17761/756685

_info

m255 13 cModel Technology dE:\farsight_fpga_course\code\high\onchip ram\quartus\simulation\modelsim va_graycounter I^2Zf5mVNijM7az`Un[kL=0 VMk:N^O83OA1@aDzHMfGYh3 w1131032666 FE:/farsight_fpga_course/
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www.eeworm.com/read/17761/757054

_info

m255 13 cModel Technology dE:\farsight_fpga_course\code\high\onchip ram\quartus\simulation\modelsim va_graycounter I^2Zf5mVNijM7az`Un[kL=0 VMk:N^O83OA1@aDzHMfGYh3 dE:\farsight_fpga_course\code\high\on
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www.eeworm.com/read/17761/757386

xrf ram_control_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/test1/ram_control.v source_file = 1
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www.eeworm.com/read/17782/760181

bld top.bld

Release 6.2i - ngdbuild G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd e:\lqj\sram+fpga+usb\дsram\usb-ram\fpga/_ngo -uc ucf.ucf -p xc3s400-p
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www.eeworm.com/read/18086/774401

hier_info mcu_sram_test.hier_info

|mcu_sram_test adstart mcu_fpga_control:inst8.clk clk => sram_control:inst4.clk clk => osc:inst2.clk clk => mfreq:freq8.clk_in wr => mcu_fpga_control:inst8.
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