mcu_sram_test.hier_info

verilog编写基于FPGA的示波器核心实现

|mcu_sram_test
adstart <= adf.DB_MAX_OUTPUT_PORT_TYPE
clk => mcu_fpga_control:inst8.clk
clk => sram_control:inst4.clk
clk => osc:inst2.clk
clk => mfreq:freq8.clk_in
wr => mcu_fpga_control:inst8.WR
rd => mcu_fpga_control:inst8.RD
cs0 => inst13.IN0
mcudata[0] <= mcu_fpga_control:inst8.databus[0]
mcudata[1] <= mcu_fpga_control:inst8.databus[1]
mcudata[2] <= mcu_fpga_control:inst8.databus[2]
mcudata[3] <= mcu_fpga_control:inst8.databus[3]
mcudata[4] <= mcu_fpga_control:inst8.databus[4]
mcudata[5] <= mcu_fpga_control:inst8.databus[5]
mcudata[6] <= mcu_fpga_control:inst8.databus[6]
mcudata[7] <= mcu_fpga_control:inst8.databus[7]
cssram => inst11.IN0
sramdata[0] <= sram_control:inst4.DATA[0]
sramdata[1] <= sram_control:inst4.DATA[1]
sramdata[2] <= sram_control:inst4.DATA[2]
sramdata[3] <= sram_control:inst4.DATA[3]
sramdata[4] <= sram_control:inst4.DATA[4]
sramdata[5] <= sram_control:inst4.DATA[5]
sramdata[6] <= sram_control:inst4.DATA[6]
sramdata[7] <= sram_control:inst4.DATA[7]
sramdata[8] <= sram_control:inst4.DATA[8]
sramdata[9] <= sram_control:inst4.DATA[9]
sramdata[10] <= sram_control:inst4.DATA[10]
sramdata[11] <= sram_control:inst4.DATA[11]
sramdata[12] <= sram_control:inst4.DATA[12]
sramdata[13] <= sram_control:inst4.DATA[13]
sramdata[14] <= sram_control:inst4.DATA[14]
sramdata[15] <= sram_control:inst4.DATA[15]
addata[0] => mux_sram:inst.data1x[0]
addata[1] => mux_sram:inst.data1x[1]
addata[2] => mux_sram:inst.data1x[2]
addata[3] => mux_sram:inst.data1x[3]
addata[4] => mux_sram:inst.data1x[4]
addata[5] => mux_sram:inst.data1x[5]
addata[6] => mux_sram:inst.data1x[6]
addata[7] => mux_sram:inst.data1x[7]
addata[8] => mux_sram:inst.data1x[8]
addata[9] => mux_sram:inst.data1x[9]
addata[10] => mux_sram:inst.data1x[10]
addata[11] => mux_sram:inst.data1x[11]
addata[12] => mux_sram:inst.data1x[12]
addata[13] => mux_sram:inst.data1x[13]
addata[14] => mux_sram:inst.data1x[14]
addata[15] => mux_sram:inst.data1x[15]
ce <= sram_control:inst4.CE
oe <= sram_control:inst4.OE
we <= sram_control:inst4.WE
LB <= <GND>
UB <= <GND>
da_wrx <= osc:inst2.da_wrx
csdis => inst10.IN0
csosc => inst9.IN0
da_wry <= osc:inst2.da_wry
A0 <= <VCC>
rdstate[0] <= mcu_fpga_control:inst8.rd_state_s[0]
rdstate[1] <= mcu_fpga_control:inst8.rd_state_s[1]
sramaddr[0] <= sram_control:inst4.ADDR[0]
sramaddr[1] <= sram_control:inst4.ADDR[1]
sramaddr[2] <= sram_control:inst4.ADDR[2]
sramaddr[3] <= sram_control:inst4.ADDR[3]
sramaddr[4] <= sram_control:inst4.ADDR[4]
sramaddr[5] <= sram_control:inst4.ADDR[5]
sramaddr[6] <= sram_control:inst4.ADDR[6]
sramaddr[7] <= sram_control:inst4.ADDR[7]
sramaddr[8] <= sram_control:inst4.ADDR[8]
sramaddr[9] <= sram_control:inst4.ADDR[9]
sramaddr[10] <= sram_control:inst4.ADDR[10]
sramaddr[11] <= sram_control:inst4.ADDR[11]
sramaddr[12] <= sram_control:inst4.ADDR[12]
sramaddr[13] <= sram_control:inst4.ADDR[13]
sramaddr[14] <= sram_control:inst4.ADDR[14]
sramaddr[15] <= sram_control:inst4.ADDR[15]
sramaddr[16] <= sram_control:inst4.ADDR[16]
state_show[0] <= stateshow[0].DB_MAX_OUTPUT_PORT_TYPE
state_show[1] <= stateshow[1].DB_MAX_OUTPUT_PORT_TYPE
state_show[2] <= stateshow[2].DB_MAX_OUTPUT_PORT_TYPE
state_show[3] <= stateshow[3].DB_MAX_OUTPUT_PORT_TYPE
x_da[0] <= osc:inst2.x_da[0]
x_da[1] <= osc:inst2.x_da[1]
x_da[2] <= osc:inst2.x_da[2]
x_da[3] <= osc:inst2.x_da[3]
x_da[4] <= osc:inst2.x_da[4]
x_da[5] <= osc:inst2.x_da[5]
x_da[6] <= osc:inst2.x_da[6]
x_da[7] <= osc:inst2.x_da[7]
y_da[0] <= osc:inst2.y_da[0]
y_da[1] <= osc:inst2.y_da[1]
y_da[2] <= osc:inst2.y_da[2]
y_da[3] <= osc:inst2.y_da[3]
y_da[4] <= osc:inst2.y_da[4]
y_da[5] <= osc:inst2.y_da[5]
y_da[6] <= osc:inst2.y_da[6]
y_da[7] <= osc:inst2.y_da[7]


|mcu_sram_test|mcu_fpga_control:inst8
clk => WBF~reg0.CLK
clk => ADF~reg0.CLK
clk => RF~reg0.CLK
clk => RBF~reg0.CLK
clk => DDSF~reg0.CLK
clk => OSCF~reg0.CLK
clk => WF~reg0.CLK
clk => wr_ca_state~2.IN1
clk => wr_dsram_state~2.IN1
clk => wr_ad_state~2.IN1
clk => rd_ca_state~2.IN1
clk => rd_dsram_state~2.IN1
clk => dds_phase_state~2.IN1
clk => dds_freq_state~2.IN1
clk => osc_mod_state~2.IN1
databus[0] <= databus~15
databus[0] <= databus~23
databus[1] <= databus~14
databus[1] <= databus~22
databus[2] <= databus~13
databus[2] <= databus~21
databus[3] <= databus~12
databus[3] <= databus~20
databus[4] <= databus~11
databus[4] <= databus~19
databus[5] <= databus~10
databus[5] <= databus~18
databus[6] <= databus~9
databus[6] <= databus~17
databus[7] <= databus~8
databus[7] <= databus~16
WR => state_show[3]~reg0.CLK
WR => state_show[2]~reg0.CLK
WR => state_show[1]~reg0.CLK
WR => state_show[0]~reg0.CLK
WR => DataBuf[15].CLK
WR => DataBuf[14].CLK
WR => DataBuf[13].CLK
WR => DataBuf[12].CLK
WR => DataBuf[11].CLK
WR => DataBuf[10].CLK
WR => DataBuf[9].CLK
WR => DataBuf[8].CLK
WR => DataBuf[7].CLK
WR => DataBuf[6].CLK
WR => DataBuf[5].CLK
WR => DataBuf[4].CLK
WR => DataBuf[3].CLK
WR => DataBuf[2].CLK
WR => DataBuf[1].CLK
WR => DataBuf[0].CLK
WR => WRDATA[15]~reg0.CLK
WR => WRDATA[14]~reg0.CLK
WR => WRDATA[13]~reg0.CLK
WR => WRDATA[12]~reg0.CLK
WR => WRDATA[11]~reg0.CLK
WR => WRDATA[10]~reg0.CLK
WR => WRDATA[9]~reg0.CLK
WR => WRDATA[8]~reg0.CLK
WR => WRDATA[7]~reg0.CLK
WR => WRDATA[6]~reg0.CLK
WR => WRDATA[5]~reg0.CLK
WR => WRDATA[4]~reg0.CLK
WR => WRDATA[3]~reg0.CLK
WR => WRDATA[2]~reg0.CLK
WR => WRDATA[1]~reg0.CLK
WR => WRDATA[0]~reg0.CLK
WR => ADDR[16]~reg0.CLK
WR => ADDR[15]~reg0.CLK
WR => ADDR[14]~reg0.CLK
WR => ADDR[13]~reg0.CLK
WR => ADDR[12]~reg0.CLK
WR => ADDR[11]~reg0.CLK
WR => ADDR[10]~reg0.CLK
WR => ADDR[9]~reg0.CLK
WR => ADDR[8]~reg0.CLK
WR => ADDR[7]~reg0.CLK
WR => ADDR[6]~reg0.CLK
WR => ADDR[5]~reg0.CLK
WR => ADDR[4]~reg0.CLK
WR => ADDR[3]~reg0.CLK
WR => ADDR[2]~reg0.CLK
WR => ADDR[1]~reg0.CLK
WR => ADDR[0]~reg0.CLK
WR => COUNT[16]~reg0.CLK
WR => COUNT[15]~reg0.CLK
WR => COUNT[14]~reg0.CLK
WR => COUNT[13]~reg0.CLK
WR => COUNT[12]~reg0.CLK
WR => COUNT[11]~reg0.CLK
WR => COUNT[10]~reg0.CLK
WR => COUNT[9]~reg0.CLK
WR => COUNT[8]~reg0.CLK
WR => COUNT[7]~reg0.CLK
WR => COUNT[6]~reg0.CLK
WR => COUNT[5]~reg0.CLK
WR => COUNT[4]~reg0.CLK
WR => COUNT[3]~reg0.CLK
WR => COUNT[2]~reg0.CLK
WR => COUNT[1]~reg0.CLK
WR => COUNT[0]~reg0.CLK
WR => MCUSramF.CLK
WR => StartADF.CLK
WR => DDSPhaseF.CLK
WR => DDSFreqF.CLK
WR => OscModF.CLK
WR => sel_mux~reg0.CLK
WR => CmdBuf[7].CLK
WR => CmdBuf[6].CLK
WR => CmdBuf[5].CLK
WR => CmdBuf[4].CLK
WR => CmdBuf[3].CLK
WR => CmdBuf[2].CLK
WR => CmdBuf[1].CLK
WR => CmdBuf[0].CLK
WR => wr_addr_is.CLK
WR => WrCountAddrF.CLK
WR => wr_count_is.CLK
WR => rd_addr_is.CLK
WR => RdCountAddrF.CLK
WR => rd_count_is.CLK
WR => wr_state~2.IN1
RD => link_rd_data_low.CLK
RD => RdSramF.CLK
RD => rd_state_s[1]~reg0.CLK
RD => rd_state_s[0]~reg0.CLK
RD => link_rd_data_high.CLK
RD => rd_state~4.IN1
CS => link_rd_data_high~0.OUTPUTSELECT
CS => rd_state~0.OUTPUTSELECT
CS => rd_state~1.OUTPUTSELECT
CS => rd_state~2.OUTPUTSELECT
CS => rd_state~3.OUTPUTSELECT
CS => rd_state_s~1.OUTPUTSELECT
CS => rd_state_s~2.OUTPUTSELECT
CS => wr_state~0.OUTPUTSELECT
CS => wr_state~1.OUTPUTSELECT
CS => state_show~0.OUTPUTSELECT
CS => state_show~1.OUTPUTSELECT
CS => state_show~2.OUTPUTSELECT
CS => state_show~3.OUTPUTSELECT
CS => DataBuf~16.OUTPUTSELECT
CS => DataBuf~17.OUTPUTSELECT
CS => DataBuf~18.OUTPUTSELECT
CS => DataBuf~19.OUTPUTSELECT
CS => DataBuf~20.OUTPUTSELECT
CS => DataBuf~21.OUTPUTSELECT
CS => DataBuf~22.OUTPUTSELECT
CS => DataBuf~23.OUTPUTSELECT
CS => DataBuf~24.OUTPUTSELECT
CS => DataBuf~25.OUTPUTSELECT
CS => DataBuf~26.OUTPUTSELECT
CS => DataBuf~27.OUTPUTSELECT
CS => DataBuf~28.OUTPUTSELECT
CS => DataBuf~29.OUTPUTSELECT
CS => DataBuf~30.OUTPUTSELECT
CS => DataBuf~31.OUTPUTSELECT
CS => WRDATA~32.OUTPUTSELECT
CS => WRDATA~33.OUTPUTSELECT
CS => WRDATA~34.OUTPUTSELECT
CS => WRDATA~35.OUTPUTSELECT
CS => WRDATA~36.OUTPUTSELECT
CS => WRDATA~37.OUTPUTSELECT
CS => WRDATA~38.OUTPUTSELECT
CS => WRDATA~39.OUTPUTSELECT
CS => WRDATA~40.OUTPUTSELECT
CS => WRDATA~41.OUTPUTSELECT
CS => WRDATA~42.OUTPUTSELECT
CS => WRDATA~43.OUTPUTSELECT
CS => WRDATA~44.OUTPUTSELECT
CS => WRDATA~45.OUTPUTSELECT
CS => WRDATA~46.OUTPUTSELECT
CS => WRDATA~47.OUTPUTSELECT
CS => ADDR~34.OUTPUTSELECT
CS => ADDR~35.OUTPUTSELECT
CS => ADDR~36.OUTPUTSELECT
CS => ADDR~37.OUTPUTSELECT
CS => ADDR~38.OUTPUTSELECT
CS => ADDR~39.OUTPUTSELECT
CS => ADDR~40.OUTPUTSELECT
CS => ADDR~41.OUTPUTSELECT
CS => ADDR~42.OUTPUTSELECT
CS => ADDR~43.OUTPUTSELECT
CS => ADDR~44.OUTPUTSELECT
CS => ADDR~45.OUTPUTSELECT
CS => ADDR~46.OUTPUTSELECT
CS => ADDR~47.OUTPUTSELECT
CS => ADDR~48.OUTPUTSELECT
CS => ADDR~49.OUTPUTSELECT
CS => ADDR~50.OUTPUTSELECT
CS => COUNT~35.OUTPUTSELECT
CS => COUNT~36.OUTPUTSELECT
CS => COUNT~37.OUTPUTSELECT
CS => COUNT~38.OUTPUTSELECT
CS => COUNT~39.OUTPUTSELECT
CS => COUNT~40.OUTPUTSELECT
CS => COUNT~41.OUTPUTSELECT
CS => COUNT~42.OUTPUTSELECT
CS => COUNT~43.OUTPUTSELECT
CS => COUNT~44.OUTPUTSELECT
CS => COUNT~45.OUTPUTSELECT
CS => COUNT~46.OUTPUTSELECT
CS => COUNT~47.OUTPUTSELECT
CS => COUNT~48.OUTPUTSELECT
CS => COUNT~49.OUTPUTSELECT
CS => COUNT~50.OUTPUTSELECT
CS => COUNT~51.OUTPUTSELECT
CS => MCUSramF.ENA
CS => StartADF.ENA
CS => DDSPhaseF.ENA
CS => DDSFreqF.ENA
CS => OscModF.ENA
CS => sel_mux~reg0.ENA
RDDATA[0] => databus~23.DATAIN
RDDATA[1] => databus~22.DATAIN
RDDATA[2] => databus~21.DATAIN
RDDATA[3] => databus~20.DATAIN
RDDATA[4] => databus~19.DATAIN
RDDATA[5] => databus~18.DATAIN
RDDATA[6] => databus~17.DATAIN
RDDATA[7] => databus~16.DATAIN
RDDATA[8] => databus~15.DATAIN
RDDATA[9] => databus~14.DATAIN
RDDATA[10] => databus~13.DATAIN
RDDATA[11] => databus~12.DATAIN
RDDATA[12] => databus~11.DATAIN
RDDATA[13] => databus~10.DATAIN
RDDATA[14] => databus~9.DATAIN
RDDATA[15] => databus~8.DATAIN
WRDATA[0] <= WRDATA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[1] <= WRDATA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[2] <= WRDATA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[3] <= WRDATA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[4] <= WRDATA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[5] <= WRDATA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[6] <= WRDATA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[7] <= WRDATA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[8] <= WRDATA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[9] <= WRDATA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[10] <= WRDATA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[11] <= WRDATA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[12] <= WRDATA[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[13] <= WRDATA[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[14] <= WRDATA[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
WRDATA[15] <= WRDATA[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[0] <= ADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[1] <= ADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[2] <= ADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[3] <= ADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[4] <= ADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[5] <= ADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ADDR[6] <= ADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE