代码搜索：CycloneII
找到约 4,731 项符合「CycloneII」的源代码
代码结果 4,731
www.eeworm.com/read/278121/4147719
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_lcell_ff is
generic(
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff"
);
por
www.eeworm.com/read/278121/4147731
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end cycloneii_and1;
www.eeworm.com/read/351808/3098768
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cycloneii_routing_
www.eeworm.com/read/351808/3098780
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_lcell_ff is
generic(
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff"
);
por
www.eeworm.com/read/351808/3098785
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_and1 is
port(
Y : out vl_logic;
IN1 : in vl_logic
);
end cycloneii_and1;
www.eeworm.com/read/492760/1171452
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONEII_PRIM_DFFE is
-- This module cannot be connected to from
-- VHDL because it has unnamed ports.
end CYCLONEII_PRIM_DFFE;
www.eeworm.com/read/466574/1510312
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONEII_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONEII_PRIM_DFFE;
www.eeworm.com/read/278121/4147723
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONEII_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONEII_PRIM_DFFE;
www.eeworm.com/read/351808/3098781
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity CYCLONEII_PRIM_DFFE is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end CYCLONEII_PRIM_DFFE;
www.eeworm.com/read/168922/9888433
bak nios32.ptf.bak
SYSTEM nios32
{
System_Wizard_Version = "5.10";
System_Wizard_Build = "176";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONEII";
clock_freq = "50000000";
gene