_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity cycloneii_and1 is
    port(
        Y               : out    vl_logic;
        IN1             : in     vl_logic
    );
end cycloneii_and1;