_primary.vhd

来自「altera fpga verilog 设计的基于查找表的DCT程序及zigza」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity CYCLONEII_PRIM_DFFE is
    // This module cannot be connected to from
    // VHDL because it has unnamed ports.
end CYCLONEII_PRIM_DFFE;