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Clock 的代码
clock_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;component cnt60 is
port(ch,cl : buffer std_logic_vector (3 downto 0);
clk : in std_logic ;
carry: buffer std_logic
);
end component
use
clock.fit.rpt
Fitter report for clock
Wed May 07 15:08:57 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fi
clock.fit.smsg
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info:
clock.tan.rpt
Timing Analyzer report for clock
Wed May 07 15:09:02 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
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1. Legal Notice
clock.fit.summary
Fitter Status : Successful - Wed May 07 15:08:57 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : Cyclone
Device : E
clock.flow.rpt
Flow report for clock
Wed May 07 15:09:02 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
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1. Legal Notice
2. Flow
clock.tan.summary
--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
clock.map.summary
Analysis & Synthesis Status : Successful - Wed May 07 15:08:53 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : Cyclo
clock.sim.rpt
Simulator report for clock
Wed Apr 09 18:06:47 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal N