clock.tan.summary

基于VHDL的电子钟 实现一个简单的电子钟

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.689 ns
From           : x
To             : show[4]~reg0
From Clock     : --
To Clock       : clk2
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.746 ns
From           : show[5]~reg0
To             : show[5]
From Clock     : clk2
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -6.208 ns
From           : x
To             : show[0]~reg0
From Clock     : --
To Clock       : clk2
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 125.83 MHz ( period = 7.947 ns )
From           : month:mo|carry2[0]
To             : day:da|dh[3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk2'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : decode[1]~reg0
To             : t[2]
From Clock     : clk2
To Clock       : clk2
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------