代码搜索：Clock
找到约 10,000 项符合「Clock」的源代码
代码结果 10,000
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sof clock.sof
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vwf clock.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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qsf clock.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
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vhd clock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock IS
port(clear:in std_logic;
clk:out STD_LOGIC);
end
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pof clock.pof
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vhd clock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port (clk:in std_logic;
en,rst:in std_logic;
th_set:in std_logic;
h_set:in std_l
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pin clock.pin
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions,
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cdf clock.cdf
/* Quartus II Version 5.0 Build 148 04/26/2005 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP1K30T144) Path("") File("clock.sof")
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hif clock.hif
Version 5.0 Build 148 04/26/2005 SJ Web Edition
2
24
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
cnt60a
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# sou
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