clock.vhd

来自「基于CYCLONG II的自己编的电子时钟.早期作品了,可能这方面的资料也比较多」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock IS
       port(clear:in std_logic;
            clk:out STD_LOGIC); 
end clock;

architecture behave of clock is
  signal temp:std_logic;
  begin
  clk<=temp;
  process(clear)
  begin
  if(clear='1')then
    temp<='0';
  elsif(temp<='0')then
    temp<='1' after 100 us;
  else
    temp<='0' after 100 us;
  END IF;
end process;
end behave;