clock.vhd

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port (clk:in std_logic;
       en,rst:in std_logic;
       th_set:in std_logic;
       h_set:in std_logic;
       tm_set:in std_logic;
       m_set:in std_logic;
       ts_set:in std_logic;
       s_set:in std_logic;
       --cout:out std_logic;
        q1l:out std_logic_vector(3 downto 0);
        q1h:out std_logic_vector(3 downto 0);
        q2l:out std_logic_vector(3 downto 0);
        q2h:out std_logic_vector(3 downto 0);
        q3l:out std_logic_vector(3 downto 0);
        q3h:out std_logic_vector(3 downto 0)
      );
end clock;
architecture behv of clock is
signal  cy1,cy2:std_logic;
signal qq1l,qq1h,qq2l,qq2h,qq3l,qq3h:std_logic_vector(3 downto 0);
component cnt_24
  port (clk:in std_logic;
       tset,set,en,rst:in std_logic;
       --cout:out std_logic;
        ql:out std_logic_vector(3 downto 0);
        qh: out std_logic_vector(3 downto 0) );
end component;
component cnt60a 
 port (clk:in std_logic;
        tset,set, en,rst:in std_logic;
      -- cout:out std_logic;
        ql:out std_logic_vector(3 downto 0);
        qh:out std_logic_vector(3 downto 0));
 end component;
component cnt60
port (clk:in std_logic;
         en,rst:in std_logic;
         tset,set:in std_logic;----
         ql:buffer std_logic_vector(3 downto 0);
        qh:buffer std_logic_vector(3 downto 0));
end component;
begin  
u1:cnt60 port map(clk=>clk,en=>en,rst=>rst,tset=>ts_set,set=>s_set,ql=>qq1l,qh=>qq1h );
u2:cnt60a port map(clk=>clk,en=>en,rst=>rst,tset=>tm_set,set=>m_set,ql=>qq2l,qh=>qq2h );
u3:cnt_24 port map(clk=>clk,en=>en,rst=>rst,tset=>th_set,set=>h_set,ql=>qq3l,qh=>qq3h);
process(clk)
begin
if clk'event and clk='1' then
 q1l<=qq1l;q1h<=qq1h;q2l<=qq2l;q2h<=qq2h;q3l<=qq3l;q3h<=qq3h;
end if;
end process;

 
end behv;