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Clock 的代码
clock.jid
. clocktop clocktop.sch d:\isptools\ispcpld\examples\cpld\mixed\clock\clocktop.sch
U9 seccntr seccntr.abl d:\isptools\ispcpld\examples\cpld\mixed\clock\seccntr.abl
U5 PRESCLR presclr.abl d:\isptools
clock.lct
[Device]
Family = LC5KVE;
PartNumber = ispLSI5128VE-80LT128I;
Package = 128TQFP;
PartType = ispLSI5128VE;
Speed = -80;
Operating_condition = IND;
Status = Production;
[Revision]
Parent =
clock.sty
[STRATEGY-LIST]
Normal=True, 976497754
clock.wet
Wave nFAST
Wave nHOLD
Wave nSLOW
Wave PM
Wave SYSCLK
Wave TEST
clock.syn
JDF B
// Created by Version 1.0
PROJECT Clock Design
DESIGN clock Normal
DEVKIT ispLSI5128VE-80LT128I
ENTRY ABEL/Schematic
STIMULUS clocktop.abv
STIMULUS clock.wdl
DOCUMENT notes.wri
MODULE
clock.wdl
%MASTERCLOCKMULT = 1;
%SMALLESTUNIT = 9;
%AUTOASSIGN = 1;
%DECIMALS = 0;
%ENDTIME = 55320;
SYSCLK { A In Default None 0 1 50 } = (0 10 1 10)#2766 ;
nSLOW { A In Default No
clock.lci
[Device]
Family = LC5KVE;
PartNumber = ispLSI5128VE-80LT128I;
Package = 128TQFP;
PartType = ispLSI5128VE;
Speed = -80;
Operating_condition = IND;
Status = Production;
[Revision]
Parent =