clock.syn

FPGA的时钟设计,源代码,很有参考价值,希望对学习FPGA设计的朋友有参考意义.

JDF B
// Created by Version 1.0 
PROJECT Clock Design
DESIGN clock Normal
DEVKIT ispLSI5128VE-80LT128I
ENTRY ABEL/Schematic
STIMULUS clocktop.abv
STIMULUS clock.wdl
DOCUMENT notes.wri
MODULE sseg.abl
MODSTYLE sseg Normal
MODULE hours.abl
MODSTYLE HOURS Normal
MODULE presclr.abl
MODSTYLE PRESCLR Normal
MODULE clocktop.sch
MODSTYLE clocktop Normal
MODULE control.sch
MODSTYLE control Normal
MODULE minutes.abl
MODSTYLE MINUTES Normal
MODULE seccntr.abl
MODSTYLE seccntr Normal