clock.wdl

FPGA的时钟设计,源代码,很有参考价值,希望对学习FPGA设计的朋友有参考意义.

%MASTERCLOCKMULT = 1;
%SMALLESTUNIT    = 9;
%AUTOASSIGN      = 1;
%DECIMALS        = 0;
%ENDTIME         = 55320;
SYSCLK { A In Default None 0 1 50 } = (0 10 1 10)#2766 ;
nSLOW { A In Default None 0 1 50 } = 1 3200 0 35200 1 16920;
nHOLD { A In Default None 0 1 50 } = 1 38400 0 6400 1 10520;
nFAST { A In Default None 0 1 50 } = 1 55320;
TEST { A In Default None 0 1 50 } = 1 55320;
COLON { A Out Default None 0 1 50 } = ;
AM { A Out Default None 0 1 50 } = ;
PM { A Out Default None 0 1 50 } = ;
HSJ { A Out Default None 0 1 50 } = ;
HSH { A Out Default None 0 1 50 } = ;
HSG { A Out Default None 0 1 50 } = ;
HSF { A Out Default None 0 1 50 } = ;
HSE { A Out Default None 0 1 50 } = ;
HSD { A Out Default None 0 1 50 } = ;
HSC { A Out Default None 0 1 50 } = ;
HSB { A Out Default None 0 1 50 } = ;
HSA { A Out Default None 0 1 50 } = ;
MTSG { A Out Default None 0 1 50 } = ;
MTSF { A Out Default None 0 1 50 } = ;
MTSE { A Out Default None 0 1 50 } = ;
MTSD { A Out Default None 0 1 50 } = ;
MTSC { A Out Default None 0 1 50 } = ;
MTSB { A Out Default None 0 1 50 } = ;
MTSA { A Out Default None 0 1 50 } = ;
MUSG { A Out Default None 0 1 50 } = ;
MUSF { A Out Default None 0 1 50 } = ;
MUSE { A Out Default None 0 1 50 } = ;
MUSD { A Out Default None 0 1 50 } = ;
MUSC { A Out Default None 0 1 50 } = ;
MUSB { A Out Default None 0 1 50 } = ;
MUSA { A Out Default None 0 1 50 } = ;