代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/18614/797310
txt program-s.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newsecond is
port (clk,reset:in std_logic;
sec1,sec2: out std_logic_vector(3 downto 0);
carry
www.eeworm.com/read/18614/797319
vhd newsecond.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newsecond is
port (clk,reset:in std_logic;
sec1,sec2: out std_logic_vector(3 downto 0);
carry
www.eeworm.com/read/18614/797340
tdf newsecond.tdf
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newsecond is
port (clk,reset:in std_logic;
sec1,sec2: out std_logic_vector(3 downto 0);
carry
www.eeworm.com/read/18614/797353
vhd newminute.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newminute is
port (carry,reset:in std_logic;
min1,min2: out std_logic_vector(3 downto 0);
car
www.eeworm.com/read/18614/797439
vhd newsencond.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newsecond is
port (clk,reset:in std_logic;
sec1,sec2: out std_logic_vector(3 downto 0);
carry
www.eeworm.com/read/18614/797454
txt program-m.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newminute is
port (carry,reset:in std_logic;
min1,min2: out std_logic_vector(3 downto 0);
car
www.eeworm.com/read/306178/3761765
c rew.c
#include
inherit NPC;
void create()
{
set_name("藏马",({"rew"}));
set("nickname", HIR"中原一点红"NOR);
set("gender", "男性");
set("age", 20);
set("long",
"他就是大侠藏马。\n");
setup();
carry_
www.eeworm.com/read/168320/9919990
vhd f4a_adder.vhd
library ieee;
use ieee.std_logic_1164.all;
entity F4a_adder is
port(a, b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0);
carry: out std_logic );
end entity;
arc
www.eeworm.com/read/165173/10073309
vhd div.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY div10 IS
PORT(clk:IN STD_ULOGIC;
carry1:OUT STD_ULOGIC
);
END div10;
ARCHITECTURE rtl OF div10 IS
www.eeworm.com/read/165173/10073647
vhd div10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY div10 IS
PORT(clk:IN STD_ULOGIC;
carry1:OUT STD_ULOGIC
);
END div10;
ARCHITECTURE rtl OF div10 IS
SIGNAL ca:STD_ULOGIC;
BEG