newminute.vhd

来自「ＦＰＧＡ数字钟的设计」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newminute is
  port (carry,reset:in std_logic;
        min1,min2: out std_logic_vector(3 downto 0);
        carrym: out std_logic);
end newminute;
architecture t1 of newminute is
signal mint1,mint2: std_logic_vector(3 downto 0);
begin
process(reset,carry)
    begin
    if reset='1' then
       mint1<="0000";
       mint2<="0000";
    elsif (carry'event and carry='1') then
        if mint1="1001" then
           mint1<="0000";
            if mint2="0101"  then
               mint2<="0000";
            else 	mint2<=mint2+1;
            end if;
        else 	mint1<=mint1+1;
        end if;
if (mint1="1001" and mint2="0101") then
            carrym<='1';
        else
            carrym<='0';
        end if;
	end if;
    end process;
        min1<=mint1;
        min2<=mint2;
end t1;