program-s.txt

ＦＰＧＡ数字钟的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newsecond is
  port (clk,reset:in std_logic;
        sec1,sec2: out std_logic_vector(3 downto 0);
        carry: out std_logic);
end newsecond;
architecture t1 of newsecond is
signal sect1,sect2: std_logic_vector(3 downto 0);
begin
process(reset,clk)
    begin
    if reset='1' then
       sect1<="0000";
       sect2<="0000";
    elsif (clk'event and clk='1') then
        if sect1="1001" then
           sect1<="0000";
            if sect2="0101"  then
               sect2<="0000";
            else 	sect2<=sect2+1;
            end if;
        else 	sect1<=sect1+1;
        end if;
if (sect1="1001" and sect2="0101") then
            carry<='1';
        else
            carry<='0';
        end if;
	end if;
    end process;
        sec1<=sect1;
        sec2<=sect2;
end t1;