f4a_adder.vhd

用VHDL写的计算器

library ieee;
use ieee.std_logic_1164.all;
entity F4a_adder is
port(a, b: in std_logic_vector(3 downto 0);
    s: out std_logic_vector(3 downto 0);
    carry: out std_logic );
end entity;

architecture Impl of F4a_adder is
  component f_adder
	port(ain, bin, cin: in std_logic;
      cout, sum: out std_logic );
  end component;

signal zero,tmp1, tmp2, tmp3: std_logic; 
begin
  u1: F_Adder port map
    (ain=>a(0), bin=>b(0), cin=>zero, cout=>tmp1, sum=>s(0));    
  u2: F_Adder port map
    (ain=>a(1), bin=>b(1), cin=>tmp1, cout=>tmp2, sum=>s(1)); 
  u3: F_Adder port map
    (ain=>a(2), bin=>b(2), cin=>tmp2, cout=>tmp3, sum=>s(2)); 
  u4: F_Adder port map
    (ain=>a(3), bin=>b(3), cin=>tmp3, cout=>carry, sum=>s(3)); 
  zero<=zero xor zero;
end architecture Impl;