代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/276500/10733788
eqn speaker.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/444607/7610838
eqn state_machine.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/433434/7930394
bak counter_16b.v.bak
module counter_16b(count0,count1,count2,count3,clock,resetb);
output [3:0] count0;
output [3:0] count1;
output [3:0] count2;
output [3:0] count3;
input clock,resetb;
wire [0:0]c1,c2,c3,c4;
reg c0=
www.eeworm.com/read/433434/7930404
v counter_16b.v
module counter_16b(count0,count1,count2,count3,clock,resetb);
output [3:0] count0;
output [3:0] count1;
output [3:0] count2;
output [3:0] count3;
input clock,resetb;
wire [0:0]c1,c2,c3,c4;
reg c0=
www.eeworm.com/read/304223/13798131
eqn wogodiv.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/482306/6622566
v myadder.v
module myadder(a,b,c,d,carry_in,sum,carry_out);
input a,b,c,d,carry_in;
output sum,carry_out;
wire a,b,carry_in;
wire sum,carry_out;
assign {carry_out,sum}=a+b+c+d+carry_in;
endmodule
www.eeworm.com/read/348172/11608489
eqn frequency_divider.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/237764/13932687
v adder4.v
module adder4(
a,
b,
carry_in,
sum,
carry_out
);
input [3:0] a,b;
input carry_in;
output [3:
www.eeworm.com/read/237764/13932814
v myadder.v
module myadder(
a,
b,
carry_in,
sum,
carry_out
);
input a,b,carry_in;
output sum,carry_out;
wi
www.eeworm.com/read/237764/13932821
v mydecr.v
module mydecr(
a,
b,
carry_in,
sum,
carry_out
);
input a,b,carry_in;
output sum,carry_out;
wir