frequency_divider.map.eqn

用VERILOG HDL实现的任意 频率分频器源代码

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--A1L3Q is Fout~reg0
--operation mode is normal

A1L3Q_lut_out = Reset_N & (A1L3Q $ (!A1L22 & !A1L32));
A1L3Q = DFFEAS(A1L3Q_lut_out, Fin, VCC, , , , , , );


--j[1] is j[1]
--operation mode is arithmetic

j[1]_carry_eqn = A1L7;
j[1]_lut_out = j[1] $ (j[1]_carry_eqn);
j[1] = DFFEAS(j[1]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L9 is j[1]~182
--operation mode is arithmetic

A1L9 = CARRY(!A1L7 # !j[1]);


--j[2] is j[2]
--operation mode is arithmetic

j[2]_carry_eqn = A1L9;
j[2]_lut_out = j[2] $ (!j[2]_carry_eqn);
j[2] = DFFEAS(j[2]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L11 is j[2]~186
--operation mode is arithmetic

A1L11 = CARRY(j[2] & (!A1L9));


--j[0] is j[0]
--operation mode is arithmetic

j[0]_lut_out = !j[0];
j[0] = DFFEAS(j[0]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L7 is j[0]~190
--operation mode is arithmetic

A1L7 = CARRY(j[0]);


--j[3] is j[3]
--operation mode is arithmetic

j[3]_carry_eqn = A1L11;
j[3]_lut_out = j[3] $ (j[3]_carry_eqn);
j[3] = DFFEAS(j[3]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L31 is j[3]~194
--operation mode is arithmetic

A1L31 = CARRY(!A1L11 # !j[3]);


--A1L22 is reduce_nor~40
--operation mode is normal

A1L22 = j[1] # j[2] # !j[3] # !j[0];


--j[4] is j[4]
--operation mode is arithmetic

j[4]_carry_eqn = A1L31;
j[4]_lut_out = j[4] $ (!j[4]_carry_eqn);
j[4] = DFFEAS(j[4]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L51 is j[4]~198
--operation mode is arithmetic

A1L51 = CARRY(j[4] & (!A1L31));


--j[5] is j[5]
--operation mode is arithmetic

j[5]_carry_eqn = A1L51;
j[5]_lut_out = j[5] $ (j[5]_carry_eqn);
j[5] = DFFEAS(j[5]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L71 is j[5]~202
--operation mode is arithmetic

A1L71 = CARRY(!A1L51 # !j[5]);


--j[6] is j[6]
--operation mode is arithmetic

j[6]_carry_eqn = A1L71;
j[6]_lut_out = j[6] $ (!j[6]_carry_eqn);
j[6] = DFFEAS(j[6]_lut_out, Fin, VCC, , , , , A1L02, );

--A1L91 is j[6]~206
--operation mode is arithmetic

A1L91 = CARRY(j[6] & (!A1L71));


--j[7] is j[7]
--operation mode is normal

j[7]_carry_eqn = A1L91;
j[7]_lut_out = j[7] $ (j[7]_carry_eqn);
j[7] = DFFEAS(j[7]_lut_out, Fin, VCC, , , , , A1L02, );


--A1L32 is reduce_nor~41
--operation mode is normal

A1L32 = j[4] # j[5] # j[6] # j[7];


--A1L02 is j[6]~213
--operation mode is normal

A1L02 = !A1L22 & !A1L32 # !Reset_N;


--Reset_N is Reset_N
--operation mode is input

Reset_N = INPUT();


--Fin is Fin
--operation mode is input

Fin = INPUT();


--Fout is Fout
--operation mode is output

Fout = OUTPUT(A1L3Q);