counter_16b.v.bak

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module counter_16b(count0,count1,count2,count3,clock,resetb);

output [3:0] count0;
output [3:0] count1;
output [3:0] count2;
output [3:0] count3;
input clock,resetb;


wire [0:0]c1,c2,c3,c4;
reg  c0=1'b1;
//reg temp;
counter_4b counter0(.count(count0),.carry_out(c1),.carry_in(c0),.clk(clock),.reset(resetb));
counter_4b # 1 counter1(.count(count1),.carry_out(c2),.carry_in(c1),.clk(clock),.reset(resetb));
counter_4b # 2 counter2(.count(count2),.carry_out(c3),.carry_in(c2),.clk(clock),.reset(resetb));
counter_4b # 3 counter3(.count(count3),.carry_out(c4),.carry_in(c3),.clk(clock),.reset(resetb));
//temp=(reg)c1;
//$display("c=%d",temp);

endmodule