代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/485060/6571876
eqn twototen.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/355947/10241060
h maths.h
extern unsigned char maths_temp;
unsigned char rotate_right(unsigned char bitrotate);
unsigned char rotate_left(unsigned char bitrotate);
#define shift_right_thru_carry(number_rotate,carry_rota
www.eeworm.com/read/391915/8372864
eqn mul.map.eqn
--A1L41 is add~10
--operation mode is normal
A1L41_carry_eqn = A1L31;
A1L41 = !A1L41_carry_eqn;
--A1L33 is add~36
--operation mode is normal
A1L33 = A1L41 & b[3];
--A1L21 is add~9
www.eeworm.com/read/178172/9416533
h idigit.h
/* DigitVecAddCarry and DigitVecSubCarry removed, RD, 14.7.93 */
/* Integer Version 2.1, RD, 13.7.93 idigit.h */
/* Changed definition of DigitMult, added DigitMultAdd, RD, 13.7.93 */
/* Integer Versi
www.eeworm.com/read/178172/9416678
h idigit.h
/* Integer Version 2.0, RD, 15.1.93 idigit.h */
/* DigitMultAdd and DigitMultSub removed, RD, 11.2.93 */
#ifndef _IDIGIT_H
#define _IDIGIT_H
#include
/* iint.h defines DigitType, BitsPerDi
www.eeworm.com/read/176099/9516678
vhdl adder_16bit_u.vhdl
-- $Id: adder_16bit_u.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Adder 16 bit
-- Project :
www.eeworm.com/read/176099/9516713
vhdl adder_18bit.vhdl
-- $Id: adder_18bit.vhdl,v 1.1.1.1 2005/01/04 02:05:58 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title : Adder 18 bit
-- Project : F
www.eeworm.com/read/421347/10740485
c div64.c
unsigned long long __udiv64(unsigned long long dividend, unsigned long long divisor)
{
unsigned long long result = dividend;
unsigned long long remainder = 0;
www.eeworm.com/read/421347/10740500
c div32.c
unsigned int __udiv32(unsigned int dividend, unsigned int divisor)
{
unsigned int result = dividend;
unsigned int remainder = 0;
unsigned int carry;
un
www.eeworm.com/read/329914/7109751
vhd month.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity month is
port( mh,ml : buffer std_logic_vector (3 downto 0);
clk : in st