month.vhd

来自「基于VHDL的电子钟 实现一个简单的电子钟」· VHDL 代码 · 共 46 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity month is 
port( 	mh,ml : buffer std_logic_vector (3 downto 0);
      	clk : in std_logic;
	    carry1: buffer std_logic;
        carry2: buffer std_logic_vector (1 downto 0));
end month;
architecture month_display of month is
begin 
  process(clk)
  begin
	if clk'event  and clk='1' then
	  if ml=9 then
		ml <="0000";
		mh <= mh+1;
		--carry2<="01";
	  elsif ml=2 then 
		if mh=1 then
		  mh <= "0000"; ml <="0001";
                  carry1 <= not carry1;
        else ml <= ml+ 1;
          carry1 <= '0';
		end if;
	  else ml <= ml+1;
              carry1 <= '0';
            if mh=0 and ml=0 then carry2<="11";
            elsif mh=0 and ml=1  then carry2<="10";
            elsif mh=0 and ml=2 then carry2<="11";
            elsif mh=0 and ml=3 then carry2<="01";
            elsif mh=0 and ml=4 then carry2<="11";
            elsif mh=0 and ml=5 then carry2<="01";
            elsif mh=0 and ml=6 then carry2<="11";
            elsif mh=0 and ml=7 then carry2<="11";
            elsif mh=0 and ml=8 then carry2<="01";
            elsif mh=0 and ml=9 then carry2<="11";
            elsif mh=1 and ml=0 then carry2<="01";
            elsif mh=1 and ml=1 then carry2<="11";
           end if;
	  end if;
    end if;
   end process;
end month_display;