代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/441731/7666319
qmsg prev_cmp_crc2.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/439953/7696697
txt gw48使用readme.txt
“MUSIC”目录"敖包相会"乐曲演奏示例使用说明
1、打开GW48-CK系统的电源；
2、下载MUSIC中的SONGER.SOF，到FPGA中；
3、用模式键选模式“1”，再按一次右侧的复位键；
4、使CLOCK9进入12MHz频率，以便控制音乐的音调；
5、使CLOCK2进入4Hz频率，以便控制音乐的节拍；
www.eeworm.com/read/198751/7912753
tlg wb_master.tlg
Selecting top level module WB_Master
Synthesizing module WB_Master
@N: CL201 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":101:0:101:5|Trying to extract state machine for registe
www.eeworm.com/read/144873/12765345
tdf l_addr_code.tdf
-- Title Statement (optional)
TITLE "80C390 Address Decoder";
CONSTANT DECODE32K = 1; % 1 == DECODE AT 0X8000 ON SEL0, 0 == DECODE AT 0X0000 ON SEL1 %
-- Subdesign Section
SU
www.eeworm.com/read/144873/12765657
tdf addrdcde.tdf
-- Title Statement (optional)
TITLE "80C390 Address Decoder";
CONSTANT DECODE32K = 1; % 1 == DECODE AT 0X8000 ON SEL0, 0 == DECODE AT 0X0000 ON SEL1 %
-- Subdesign Section
SU
www.eeworm.com/read/140983/13049056
ucf top.ucf
#####################
# clock constraints #
#####################
#
#specifying clock periods
#133 MHz
NET "sys_clk" PERIOD = 7.5ns ;
NET "fpga_clk" PERIOD = 7.5ns ;
NET "fpga_clk2x" PERIOD
www.eeworm.com/read/326648/13127238
qmsg rec.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
www.eeworm.com/read/326648/13128297
qmsg txd.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
www.eeworm.com/read/326319/13147700
v usbrefdesign.v
module USBRefDesign(
//系统信号
input wire sclk, //sclk为FPGA工作时钟,默认100MHz.
//FPGA和FT245MB间的USB接口
input wire USB_RXE,
output reg USB_RD,
input wire [7
www.eeworm.com/read/137360/13326693
txt gw48使用readme.txt
“PINPAN”目录乒乓游戏示例使用说明
1、打开GW48系统的电源；
2、下载PINPAN中的TABLETENNIS.SOF，到FPGA EPF10K10中；
3、用模式键选模式“3”，再按一次右侧的复位键；
4、使CLOCK5进入1024Hz频率,以便听到出错时的鸣叫；
5、使CLOCK2进入4Hz频率，以