l_addr_code.tdf

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).

--  Title Statement (optional)
TITLE "80C390 Address Decoder";

CONSTANT DECODE32K = 1;                 % 1 == DECODE AT 0X8000 ON SEL0, 0 == DECODE AT 0X0000 ON SEL1 %

--  Subdesign Section
SUBDESIGN l_addr_code
(
        addr[6..0], addr15, SEL0_N, SEL1_N, RESET_N  : INPUT;
        RAM_SEL_N,  FPGA_SEL_N                       : OUTPUT;
)

--  Logic Section
BEGIN

        DEFAULTS
                RAM_SEL_N = 1;
                FPGA_SEL_N = 1;
        END DEFAULTS;

        --  Truth Table Statement
IF DECODE32K == 1 GENERATE
TABLE
        ADDR[6..0],  addr15, RESET_N, SEL0_N, SEL1_N   => RAM_SEL_N, FPGA_SEL_N;

        B"XXXXXXX",     X,      1,       X,      X      =>  1,             1;  % no selects during RESET %

        B"XXXXXXX",     X,      0,       1,      1      =>  1,             1;  % no selects WHEN NOT SELECTED %
        B"XXXXXXX",     X,      0,       0,      0      =>  1,             1;  % no selects WHEN SELECTED TO MUCH %
   % Ram select %
        B"XXXXXXX",     0,      0,       0,      1      =>  0,             1;  % RAM SELECT %
   % Memory Mapped IO %
   %  Mapped to 0x8000 on SEL 0 %
        B"XXX0000",     1,      0,       0,      1      =>  1,             0;  % Port  0 %   % Select 0 %
        B"XXX0001",     1,      0,       0,      1      =>  1,             0;  % Port  1 %
        B"XXX0010",     1,      0,       0,      1      =>  1,             0;  % Port  2 %
        B"XXX0011",     1,      0,       0,      1      =>  1,             0;  % Port  3 %
        B"XXX0100",     1,      0,       0,      1      =>  1,             0;  % Port  4 %
        B"XXX0101",     1,      0,       0,      1      =>  1,             0;  % Port  5 %
        B"XXX0110",     1,      0,       0,      1      =>  1,             0;  % Port  6 %
        B"XXX0111",     1,      0,       0,      1      =>  1,             0;  % Port  7 %
        B"XXX1000",     1,      0,       0,      1      =>  1,             0;  % Port  8 %
        B"XXX1001",     1,      0,       0,      1      =>  1,             0;  % Port  9 %
        B"XXX1010",     1,      0,       0,      1      =>  1,             0;  % Port 10 %
        B"XXX1011",     1,      0,       0,      1      =>  1,             0;  % Port 11 %
        B"XXX1100",     1,      0,       0,      1      =>  1,             0;  % Port 12 %
        B"XXX1101",     1,      0,       0,      1      =>  1,             0;  % Port 12 %
        B"XXX111X",     1,      0,       0,      1      =>  1,             0;  % Port 12 %
END TABLE;
ELSE GENERATE
TABLE
        ADDR[6..0], ADDR15, RESET_N, SEL0_N, SEL1_N   =>  RAM_SEL_N,FPGA_SEL_N;

        B"XXXXX",     X,      1,       X,      X      =>  1,             1;  % no selects during RESET %

        B"XXXXX",     X,      0,       1,      1      =>  1,             1;  % no selects WHEN NOT SELECTED %
        B"XXXXX",     X,      0,       0,      0      =>  1,             1;  % no selects WHEN SELECTED TO MUCH %
   % Ram select %
        B"XXXXX",     X,      0,       0,      1      =>  0,             1;  % RAM SELECT %
   % Memory Mapped IO %
   %  Mapped to 0x0000 on SEL 1 %
        B"X0000",     X,      0,       1,      0      =>  1,             0;  % Port  0 %   % Select 1 %
        B"X0001",     X,      0,       1,      0      =>  1,             0;  % Port  1 %
        B"X0010",     X,      0,       1,      0      =>  1,             0;  % Port  2 %
        B"X0011",     X,      0,       1,      0      =>  1,             0;  % Port  3 %
        B"X0100",     X,      0,       1,      0      =>  1,             0;  % Port  4 %
        B"X0101",     X,      0,       1,      0      =>  1,             0;  % Port  5 %
        B"X0110",     X,      0,       1,      0      =>  1,             0;  % Port  6 %
        B"X0111",     X,      0,       1,      0      =>  1,             0;  % Port  7 %
        B"X1000",     X,      0,       1,      0      =>  1,             0;  % Port  8 %
        B"X1001",     X,      0,       1,      0      =>  1,             0;  % Port  9 %
        B"X1010",     X,      0,       1,      0      =>  1,             0;  % Port 10 %
        B"X1011",     X,      0,       1,      0      =>  1,             0;  % Port 11 %
        B"X1100",     1,      0,       1,      0      =>  1,             0;  % Port 12 %
        B"X1101",     1,      0,       1,      0      =>  1,             0;  % Port 12 %
        B"X111X",     1,      0,       1,      0      =>  1,             0;  % Port 12 %
END TABLE;
END GENERATE;

END;