代码搜索：CASE
找到约 10,000 项符合「CASE」的源代码
代码结果 10,000
www.eeworm.com/read/130737/7112135
bmp p_case.bmp
www.eeworm.com/read/450207/7152466
v mux_case.v
module mux_case(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
always @(in0 or in1 or in2 or in3 or sel)
begin
case(sel)
2'b00: out=in0;
2'b01: out=
www.eeworm.com/read/462280/7203636
gif case_left.gif
www.eeworm.com/read/462280/7203694
gif case_right.gif
www.eeworm.com/read/460669/7243928
vhd case1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case1 IS
PORT ( table_in:in std_logic_vector(3 downto 0);
table_out:out integer range -10 to 70);
END case1;
ARCHITECTURE behave OF case
www.eeworm.com/read/460669/7243929
vhd case2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case2 IS
PORT ( table_in:in std_logic_vector(3 downto 0);
table_out:out integer range -150 to 100);
END case2;
ARCHITECTURE behave OF ca
www.eeworm.com/read/460669/7243931
vhd case3.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case3 IS
PORT ( table_in:in std_logic_vector(3 downto 0);
table_out:out integer range -550 to 200);
END case3;
ARCHITECTURE behave OF ca
www.eeworm.com/read/460669/7243932
vhd case4.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case4 IS
PORT ( table_in:in std_logic_vector(3 downto 0);
table_out:out integer range 0 to 4600);
END case4;
ARCHITECTURE behave OF case
www.eeworm.com/read/458682/7291673
sh case-cmd.sh
#!/bin/bash
# case-cmd.sh: Using command substitution to generate a "case" variable.
case $( arch ) in # "arch" returns machine architecture.
# Equivalent to 'uname -m' ...
i3
www.eeworm.com/read/456603/7343817
v mux_case.v
module mux_case(out,in0,in1,in2,in3,sel);
output out;
input in0,in1,in2,in3;
input[1:0] sel;
reg out;
always @(in0 or in1 or in2 or in3 or sel)
begin
case(sel)
2'b00: out=in0;
2'b01: out=