case2.vhd

来自「DA算法中的使用的查找表模块」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case2  IS
PORT ( table_in:in std_logic_vector(3 downto 0);
       table_out:out integer range -150 to 100);
END case2;
ARCHITECTURE behave OF case2 IS
BEGIN
  PROCESS (table_in)
    BEGIN
      case table_in is
           when "0000"=>table_out<=0;
           when "0001"=>table_out<=41;
           when "0010"=>table_out<=23;
           when "0011"=>table_out<=64;
           when "0100"=>table_out<=-32;
           when "0101"=>table_out<=9;
           when "0110"=>table_out<=-9;
           when "0111"=>table_out<=32;
           when "1000"=>table_out<=-117;
           when "1001"=>table_out<=-76;
           when "1010"=>table_out<=-94;
           when "1011"=>table_out<=-53;
           when "1100"=>table_out<=-149;
           when "1101"=>table_out<=-108;
           when "1110"=>table_out<=-126;
           when "1111"=>table_out<=-85;
           when others=>table_out<=0;

      end case;
  END PROCESS;
END behave;