case4.vhd

来自「DA算法中的使用的查找表模块」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case4  IS
PORT ( table_in:in std_logic_vector(3 downto 0);
       table_out:out integer range 0 to 4600);
END case4;
ARCHITECTURE behave OF case4 IS
BEGIN
  PROCESS (table_in)
    BEGIN
      case table_in is
           when "0000"=>table_out<=0;
           when "0001"=>table_out<=536;
           when "0010"=>table_out<=983;
           when "0011"=>table_out<=1519;
           when "0100"=>table_out<=1377;
           when "0101"=>table_out<=1913;
           when "0110"=>table_out<=2360;
           when "0111"=>table_out<=2896;
           when "1000"=>table_out<=1609;
           when "1001"=>table_out<=2145;
           when "1010"=>table_out<=2592;
           when "1011"=>table_out<=3128;
           when "1100"=>table_out<=2986;
           when "1101"=>table_out<=3522;
           when "1110"=>table_out<=3969;
           when "1111"=>table_out<=4505;
           when others=>table_out<=0;

      end case;
  END PROCESS;
END behave;