case1.vhd

来自「DA算法中的使用的查找表模块」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY case1  IS
PORT ( table_in:in std_logic_vector(3 downto 0);
       table_out:out integer range -10 to 70);
END case1;
ARCHITECTURE behave OF case1 IS
BEGIN
  PROCESS (table_in)
    BEGIN
      case table_in is
           when "0000"=>table_out<=0;
           when "0001"=>table_out<=-4;
           when "0010"=>table_out<=5;
           when "0011"=>table_out<=1;
           when "0100"=>table_out<=19;
           when "0101"=>table_out<=15;
           when "0110"=>table_out<=24;
           when "0111"=>table_out<=20;
           when "1000"=>table_out<=34;
           when "1001"=>table_out<=30;
           when "1010"=>table_out<=39;
           when "1011"=>table_out<=35;
           when "1100"=>table_out<=53;
           when "1101"=>table_out<=49;
           when "1110"=>table_out<=58;
           when "1111"=>table_out<=54;
           when others=>table_out<=0;

      end case;
  END PROCESS;
END behave;