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C 的代码
consist.h
#define C_BELL 00 //报时声
#define C_NOW 01 //现在时刻
#define C_LINGCHEN 02 //凌晨
#define C_NOON 03 //上午
#define C_AFTERNOON 04 //下午
#define C_NIG
rel.tab
A B C
a1 b1 c1
a1 b1 c2
a2 b1 c1
a2 b1 c2
a2 b3 c2
a2 b3 c3
a3 b2 c2
a4 b2 c2
a4 b3 c2
a4 b3 c3
statusc2f.c
/* -*- Mode: C; c-basic-offset:4 ; -*- */
/*
* (C) 2001 by Argonne National Laboratory.
* See COPYRIGHT in top-level directory.
*
* This file is automatically generated by buildiface
*
resonvc.alg
(RESONVC-ALG
(NAME "resonvc")
(ARGUMENTS ("sound_type" "s1") ("sound_type" "hz") ("double" "bw")
("int" "normalization"))
(INLINE-INTERPOLATION T)
(INTERNAL-SCALING s1)
(ALWAYS-SCALE hz)
(S
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_dist_mem_v4_1 is
generic(
c_addr_width : integer := 6;
c_default_data : string := "0";
c_default_data_radix: intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_dist_mem_v4_0 is
generic(
c_addr_width : integer := 6;
c_default_data : string := "0";
c_default_data_radix: intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_dist_mem_v3_0 is
generic(
c_addr_width : integer := 6;
c_default_data : string := "0";
c_default_data_radix: intege
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity c_mem_dp_block_v1_0 is
generic(
c_address_width_a: integer := 12;
c_address_width_b: integer := 12;
c_clka_polarity : inte
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mac_delay_control_v1_1_v is
generic(
c_a_type : integer := 0;
c_a_width : integer := 1;
c_b_mode : int
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mac_delay_control_v1_0_v is
generic(
c_a_type : integer := 0;
c_a_width : integer := 1;
c_b_mode : int