_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity c_mem_dp_block_v1_0 is
    generic(
        c_address_width_a: integer := 12;
        c_address_width_b: integer := 12;
        c_clka_polarity : integer := 1;
        c_clkb_polarity : integer := 1;
        c_default_data  : string  := "0";
        c_depth_a       : integer := 4096;
        c_depth_b       : integer := 4096;
        c_ena_polarity  : integer := 1;
        c_enb_polarity  : integer := 1;
        c_generate_mif  : integer := 0;
        c_has_dia       : integer := 1;
        c_has_dib       : integer := 1;
        c_has_doa       : integer := 1;
        c_has_dob       : integer := 1;
        c_has_ena       : integer := 1;
        c_has_enb       : integer := 1;
        c_has_rsta      : integer := 1;
        c_has_rstb      : integer := 1;
        c_has_wea       : integer := 1;
        c_has_web       : integer := 1;
        c_mem_init_file : string  := "null.mif";
        c_mem_init_radix: integer := 2;
        c_pipe_stages   : integer := 0;
        c_read_mif      : integer := 1;
        c_rsta_polarity : integer := 1;
        c_rstb_polarity : integer := 1;
        c_wea_polarity  : integer := 1;
        c_web_polarity  : integer := 1;
        c_width_a       : integer := 1;
        c_width_b       : integer := 1
    );
    port(
        ena             : in     vl_logic;
        enb             : in     vl_logic;
        wea             : in     vl_logic;
        web             : in     vl_logic;
        rsta            : in     vl_logic;
        rstb            : in     vl_logic;
        clka            : in     vl_logic;
        clkb            : in     vl_logic;
        addra           : in     vl_logic_vector;
        addrb           : in     vl_logic_vector;
        dia             : in     vl_logic_vector;
        dib             : in     vl_logic_vector;
        doa             : out    vl_logic_vector;
        dob             : out    vl_logic_vector
    );
end c_mem_dp_block_v1_0;